[mips][ias] Implement macro expansion when bcc has an immediate where a register belongs.
Summary: Fixes PR24915. Reviewers: vkalintiris Subscribers: emaste, seanbruno, llvm-commits Differential Revision: http://reviews.llvm.org/D13533 llvm-svn: 250042
This commit is contained in:
Daniel Sanders
parent
332cef6c5f
commit
b1ef88c172
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@ -1937,6 +1937,22 @@ bool MipsAsmParser::needsExpansion(MCInst &Inst) {
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case Mips::BLEUL:
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case Mips::BGEUL:
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case Mips::BGTUL:
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case Mips::BLTImmMacro:
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case Mips::BLEImmMacro:
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case Mips::BGEImmMacro:
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case Mips::BGTImmMacro:
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case Mips::BLTUImmMacro:
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case Mips::BLEUImmMacro:
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case Mips::BGEUImmMacro:
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case Mips::BGTUImmMacro:
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case Mips::BLTLImmMacro:
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case Mips::BLELImmMacro:
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case Mips::BGELImmMacro:
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case Mips::BGTLImmMacro:
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case Mips::BLTULImmMacro:
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case Mips::BLEULImmMacro:
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case Mips::BGEULImmMacro:
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case Mips::BGTULImmMacro:
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case Mips::SDivMacro:
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case Mips::UDivMacro:
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case Mips::DSDivMacro:
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@ -2028,6 +2044,22 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
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case Mips::BLEUL:
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case Mips::BGEUL:
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case Mips::BGTUL:
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case Mips::BLTImmMacro:
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case Mips::BLEImmMacro:
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case Mips::BGEImmMacro:
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case Mips::BGTImmMacro:
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case Mips::BLTUImmMacro:
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case Mips::BLEUImmMacro:
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case Mips::BGEUImmMacro:
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case Mips::BGTUImmMacro:
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case Mips::BLTLImmMacro:
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case Mips::BLELImmMacro:
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case Mips::BGELImmMacro:
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case Mips::BGTLImmMacro:
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case Mips::BLTULImmMacro:
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case Mips::BLEULImmMacro:
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case Mips::BGEULImmMacro:
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case Mips::BGTULImmMacro:
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return expandCondBranches(Inst, IDLoc, Instructions);
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case Mips::SDivMacro:
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return expandDiv(Inst, IDLoc, Instructions, false, true);
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@ -2614,14 +2646,84 @@ MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
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bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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bool EmittedNoMacroWarning = false;
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unsigned PseudoOpcode = Inst.getOpcode();
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unsigned SrcReg = Inst.getOperand(0).getReg();
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unsigned TrgReg = Inst.getOperand(1).getReg();
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const MCOperand &TrgOp = Inst.getOperand(1);
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const MCExpr *OffsetExpr = Inst.getOperand(2).getExpr();
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unsigned ZeroSrcOpcode, ZeroTrgOpcode;
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bool ReverseOrderSLT, IsUnsigned, IsLikely, AcceptsEquality;
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unsigned TrgReg;
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if (TrgOp.isReg())
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TrgReg = TrgOp.getReg();
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else if (TrgOp.isImm()) {
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warnIfNoMacro(IDLoc);
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EmittedNoMacroWarning = true;
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TrgReg = getATReg(IDLoc);
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if (!TrgReg)
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return true;
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switch(PseudoOpcode) {
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default:
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llvm_unreachable("unknown opcode for branch pseudo-instruction");
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case Mips::BLTImmMacro:
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PseudoOpcode = Mips::BLT;
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break;
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case Mips::BLEImmMacro:
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PseudoOpcode = Mips::BLE;
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break;
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case Mips::BGEImmMacro:
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PseudoOpcode = Mips::BGE;
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break;
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case Mips::BGTImmMacro:
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PseudoOpcode = Mips::BGT;
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break;
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case Mips::BLTUImmMacro:
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PseudoOpcode = Mips::BLTU;
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break;
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case Mips::BLEUImmMacro:
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PseudoOpcode = Mips::BLEU;
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break;
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case Mips::BGEUImmMacro:
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PseudoOpcode = Mips::BGEU;
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break;
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case Mips::BGTUImmMacro:
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PseudoOpcode = Mips::BGTU;
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break;
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case Mips::BLTLImmMacro:
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PseudoOpcode = Mips::BLTL;
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break;
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case Mips::BLELImmMacro:
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PseudoOpcode = Mips::BLEL;
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break;
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case Mips::BGELImmMacro:
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PseudoOpcode = Mips::BGEL;
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break;
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case Mips::BGTLImmMacro:
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PseudoOpcode = Mips::BGTL;
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break;
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case Mips::BLTULImmMacro:
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PseudoOpcode = Mips::BLTUL;
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break;
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case Mips::BLEULImmMacro:
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PseudoOpcode = Mips::BLEUL;
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break;
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case Mips::BGEULImmMacro:
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PseudoOpcode = Mips::BGEUL;
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break;
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case Mips::BGTULImmMacro:
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PseudoOpcode = Mips::BGTUL;
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break;
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}
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if (loadImmediate(TrgOp.getImm(), TrgReg, Mips::NoRegister, !isGP64bit(),
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false, IDLoc, Instructions))
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return true;
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}
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switch (PseudoOpcode) {
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case Mips::BLT:
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case Mips::BLTU:
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@ -2770,7 +2872,8 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
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if (!ATRegNum)
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return true;
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warnIfNoMacro(IDLoc);
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if (!EmittedNoMacroWarning)
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warnIfNoMacro(IDLoc);
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// SLT fits well with 2 of our 4 pseudo-branches:
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// BLT, where $rs < $rt, translates into "slt $at, $rs, $rt" and
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@ -1809,6 +1809,27 @@ def BLEUL: CondBranchPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
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def BGEUL: CondBranchPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
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def BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
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class CondBranchImmPseudo<string instr_asm> :
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MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, imm64:$imm, brtarget:$offset),
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!strconcat(instr_asm, "\t$rs, $imm, $offset")>;
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def BLTImmMacro : CondBranchImmPseudo<"blt">;
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def BLEImmMacro : CondBranchImmPseudo<"ble">;
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def BGEImmMacro : CondBranchImmPseudo<"bge">;
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def BGTImmMacro : CondBranchImmPseudo<"bgt">;
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def BLTUImmMacro : CondBranchImmPseudo<"bltu">;
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def BLEUImmMacro : CondBranchImmPseudo<"bleu">;
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def BGEUImmMacro : CondBranchImmPseudo<"bgeu">;
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def BGTUImmMacro : CondBranchImmPseudo<"bgtu">;
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def BLTLImmMacro : CondBranchImmPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;
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def BLELImmMacro : CondBranchImmPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;
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def BGELImmMacro : CondBranchImmPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;
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def BGTLImmMacro : CondBranchImmPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;
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def BLTULImmMacro : CondBranchImmPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;
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def BLEULImmMacro : CondBranchImmPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
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def BGEULImmMacro : CondBranchImmPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
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def BGTULImmMacro : CondBranchImmPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
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// FIXME: Predicates are removed because instructions are matched regardless of
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// predicates, because PredicateControl was not in the hierarchy. This was
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// done to emit more precise error message from expansion function.
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@ -0,0 +1,12 @@
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# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
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# RUN: FileCheck %s --check-prefix=ALL
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.text
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.set noat
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foo:
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blt $a2, 16, foo # ALL: :[[@LINE]]:5: error: pseudo-instruction requires $at, which is not available
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.set at
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.set noreorder
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.set nomacro
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blt $a2, 16, foo # ALL: :[[@LINE]]:5: warning: macro instruction expanded into multiple instructions
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# ALL-NOT: :[[@LINE-1]]:5: warning: macro instruction expanded into multiple instructions
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@ -0,0 +1,69 @@
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# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -show-encoding 2>&1 | \
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# RUN: FileCheck %s --check-prefix=ALL
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.text
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foo: # ALL-LABEL: foo:
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blt $a2, 16, foo # ALL: addiu $1, $zero, 16
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# ALL: slt $1, $6, $1
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# ALL: bnez $1, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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ble $a2, 16, foo # ALL: addiu $1, $zero, 16
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# ALL: slt $1, $1, $6
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# ALL: beqz $1, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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bge $a2, 32767, foo # ALL: addiu $1, $zero, 32767
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# ALL: slt $1, $6, $1
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# ALL: beqz $1, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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bgt $a2, 32768, foo # ALL: ori $1, $zero, 32768
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# ALL: slt $1, $1, $6
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# ALL: bnez $1, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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bltu $a2, 16, foo # ALL: addiu $1, $zero, 16
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# ALL: sltu $1, $6, $1
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# ALL: bnez $1, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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bleu $a2, 16, foo # ALL: addiu $1, $zero, 16
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# ALL: sltu $1, $1, $6
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# ALL: beqz $1, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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bgeu $a2, 32767, foo # ALL: addiu $1, $zero, 32767
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# ALL: sltu $1, $6, $1
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# ALL: beqz $1, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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bgtu $a2, 32768, foo # ALL: ori $1, $zero, 32768
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# ALL: sltu $1, $1, $6
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# ALL: bnez $1, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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bltl $a2, 16, foo # ALL: addiu $1, $zero, 16
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# ALL: slt $1, $6, $1
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# ALL: bnel $1, $zero, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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blel $a2, 16, foo # ALL: addiu $1, $zero, 16
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# ALL: slt $1, $1, $6
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# ALL: beql $1, $zero, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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bgel $a2, 32767, foo # ALL: addiu $1, $zero, 32767
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# ALL: slt $1, $6, $1
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# ALL: beql $1, $zero, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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bgtl $a2, 32768, foo # ALL: ori $1, $zero, 32768
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# ALL: slt $1, $1, $6
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# ALL: bnel $1, $zero, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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bltul $a2, 16, foo # ALL: addiu $1, $zero, 16
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# ALL: sltu $1, $6, $1
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# ALL: bnel $1, $zero, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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bleul $a2, 16, foo # ALL: addiu $1, $zero, 16
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# ALL: sltu $1, $1, $6
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# ALL: beql $1, $zero, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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bgeul $a2, 32767, foo # ALL: addiu $1, $zero, 32767
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# ALL: sltu $1, $6, $1
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# ALL: beql $1, $zero, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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bgtul $a2, 65536, foo # ALL: lui $1, 1
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# ALL: sltu $1, $1, $6
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# ALL: bnel $1, $zero, foo
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# ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
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