[MIParser] Ensure getHexUint doesn't produce APInts with a bitwidth of 0

If getHexUint reads in a hex 0, it will create an APInt with a value of 0.
The number of active bits on this APInt is used to calculate the bitwidth of
Result. The number of active bits is defined as an APInt's bitwidth - its
number of leading 0s. Since this APInt is 0, its bitwidth and number of leading
0s are equal.

Thus, Result is constructed with a bitwidth of 0, triggering an APInt assert.

This commit fixes that by checking if the APInt is equal to 0, and setting the
bitwidth to 32 if it is. Otherwise, it sets the bitwidth using getActiveBits.

This caused issues when compiling MIR files with successor probabilities. In
the case that a successor is tagged with a probability of 0, this assert would
fire on debug builds.

https://reviews.llvm.org/D37401

llvm-svn: 312387

llvm/lib/CodeGen/MIRParser/MIParser.cpp

@@ -2083,8 +2083,11 @@ bool MIParser::getHexUint(APInt &Result) {
     return true;
   StringRef V = S.substr(2);
   APInt A(V.size()*4, V, 16);
-  Result = APInt(A.getActiveBits(),
-                 ArrayRef<uint64_t>(A.getRawData(), A.getNumWords()));
+
+  // If A is 0, then A.getActiveBits() is 0. This isn't a valid bitwidth. Make
+  // sure it isn't the case before constructing result.
+  unsigned NumBits = (A == 0) ? 32 : A.getActiveBits();
+  Result = APInt(NumBits, ArrayRef<uint64_t>(A.getRawData(), A.getNumWords()));
   return false;
 }
 

llvm/test/CodeGen/Generic/zero-probability.mir

@@ -0,0 +1,39 @@
+# RUN: llc -o /dev/null %s 
+# REQUIRES: asserts
+# Makes sure that having a probability of 0x00000000 to branch to a successor
+# doesn't hit an APInt assert in the MIParser.
+
+--- |
+  define i32 @main() local_unnamed_addr #0 {
+  entry:
+    ret i32 0
+  
+  other:
+    ret i32 0
+  }
+  
+  attributes #0 = { nounwind }
+  
+  !llvm.module.flags = !{!0, !1}
+  !llvm.ident = !{!2}
+  
+  !0 = !{i32 1, !"wchar_size", i32 4}
+  !1 = !{i32 7, !"PIC Level", i32 2}
+  !2 = !{!"clang version 6.0.0"}
+  !3 = !{!"branch_weights", i32 0, i32 -1}
+
+...
+---
+name:            main
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true   
+body:             |
+  bb.0.entry:
+    successors: %bb.1.other(0x00000000)
+  bb.1.other:
+
+...