[AVX-512] Add test cases that demonstrate some patterns that don't work correctly in 32-bit mode. NFC
llvm-svn: 297706
This commit is contained in:
Craig Topper
parent
a48ea231c0
commit
b0a82eaea6
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@ -1,12 +1,22 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -O2 -mattr=avx512f -mtriple=x86_64-unknown | FileCheck %s
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; RUN: llc < %s -O2 -mattr=avx512f -mtriple=x86_64-unknown | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK64
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; RUN: llc < %s -O2 -mattr=avx512f -mtriple=i386-unknown | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK32
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define <4 x float> @test_mm_mask_move_ss(<4 x float> %__W, i8 zeroext %__U, <4 x float> %__A, <4 x float> %__B) local_unnamed_addr #0 {
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; CHECK-LABEL: test_mm_mask_move_ss:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovss %xmm2, %xmm1, %xmm0 {%k1}
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; CHECK-NEXT: retq
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; CHECK64-LABEL: test_mm_mask_move_ss:
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; CHECK64: # BB#0: # %entry
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; CHECK64-NEXT: kmovw %edi, %k1
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; CHECK64-NEXT: vmovss %xmm2, %xmm1, %xmm0 {%k1}
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; CHECK64-NEXT: retq
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;
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; CHECK32-LABEL: test_mm_mask_move_ss:
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; CHECK32: # BB#0: # %entry
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; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al
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; CHECK32-NEXT: andl $1, %eax
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; CHECK32-NEXT: kmovw %eax, %k1
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; CHECK32-NEXT: vmovss %xmm2, %xmm0, %xmm0 {%k1}
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; CHECK32-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; CHECK32-NEXT: retl
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entry:
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%0 = and i8 %__U, 1
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%tobool.i = icmp ne i8 %0, 0
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@ -18,11 +28,21 @@ entry:
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}
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define <4 x float> @test_mm_maskz_move_ss(i8 zeroext %__U, <4 x float> %__A, <4 x float> %__B) local_unnamed_addr #0 {
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; CHECK-LABEL: test_mm_maskz_move_ss:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} {z}
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; CHECK-NEXT: retq
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; CHECK64-LABEL: test_mm_maskz_move_ss:
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; CHECK64: # BB#0: # %entry
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; CHECK64-NEXT: kmovw %edi, %k1
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; CHECK64-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} {z}
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; CHECK64-NEXT: retq
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;
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; CHECK32-LABEL: test_mm_maskz_move_ss:
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; CHECK32: # BB#0: # %entry
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; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al
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; CHECK32-NEXT: andl $1, %eax
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; CHECK32-NEXT: kmovw %eax, %k1
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; CHECK32-NEXT: vxorps %xmm2, %xmm2, %xmm2
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; CHECK32-NEXT: vmovss %xmm1, %xmm0, %xmm2 {%k1}
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; CHECK32-NEXT: vmovss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
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; CHECK32-NEXT: retl
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entry:
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%0 = and i8 %__U, 1
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%tobool.i = icmp ne i8 %0, 0
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@ -33,11 +53,20 @@ entry:
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}
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define <2 x double> @test_mm_mask_move_sd(<2 x double> %__W, i8 zeroext %__U, <2 x double> %__A, <2 x double> %__B) local_unnamed_addr #0 {
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; CHECK-LABEL: test_mm_mask_move_sd:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovsd %xmm2, %xmm1, %xmm0 {%k1}
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; CHECK-NEXT: retq
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; CHECK64-LABEL: test_mm_mask_move_sd:
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; CHECK64: # BB#0: # %entry
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; CHECK64-NEXT: kmovw %edi, %k1
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; CHECK64-NEXT: vmovsd %xmm2, %xmm1, %xmm0 {%k1}
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; CHECK64-NEXT: retq
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;
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; CHECK32-LABEL: test_mm_mask_move_sd:
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; CHECK32: # BB#0: # %entry
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; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al
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; CHECK32-NEXT: andl $1, %eax
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; CHECK32-NEXT: kmovw %eax, %k1
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; CHECK32-NEXT: vmovsd %xmm2, %xmm0, %xmm0 {%k1}
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; CHECK32-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
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; CHECK32-NEXT: retl
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entry:
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%0 = and i8 %__U, 1
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%tobool.i = icmp ne i8 %0, 0
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@ -49,11 +78,21 @@ entry:
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}
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define <2 x double> @test_mm_maskz_move_sd(i8 zeroext %__U, <2 x double> %__A, <2 x double> %__B) local_unnamed_addr #0 {
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; CHECK-LABEL: test_mm_maskz_move_sd:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1} {z}
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; CHECK-NEXT: retq
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; CHECK64-LABEL: test_mm_maskz_move_sd:
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; CHECK64: # BB#0: # %entry
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; CHECK64-NEXT: kmovw %edi, %k1
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; CHECK64-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1} {z}
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; CHECK64-NEXT: retq
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;
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; CHECK32-LABEL: test_mm_maskz_move_sd:
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; CHECK32: # BB#0: # %entry
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; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al
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; CHECK32-NEXT: andl $1, %eax
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; CHECK32-NEXT: kmovw %eax, %k1
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; CHECK32-NEXT: vxorpd %xmm2, %xmm2, %xmm2
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; CHECK32-NEXT: vmovsd %xmm1, %xmm0, %xmm2 {%k1}
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; CHECK32-NEXT: vmovsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
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; CHECK32-NEXT: retl
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entry:
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%0 = and i8 %__U, 1
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%tobool.i = icmp ne i8 %0, 0
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@ -64,11 +103,22 @@ entry:
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}
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define void @test_mm_mask_store_ss(float* %__W, i8 zeroext %__U, <4 x float> %__A) local_unnamed_addr #1 {
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; CHECK-LABEL: test_mm_mask_store_ss:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %esi, %k1
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; CHECK-NEXT: vmovss %xmm0, (%rdi) {%k1}
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; CHECK-NEXT: retq
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; CHECK64-LABEL: test_mm_mask_store_ss:
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; CHECK64: # BB#0: # %entry
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; CHECK64-NEXT: kmovw %esi, %k1
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; CHECK64-NEXT: vmovss %xmm0, (%rdi) {%k1}
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; CHECK64-NEXT: retq
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;
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; CHECK32-LABEL: test_mm_mask_store_ss:
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; CHECK32: # BB#0: # %entry
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; CHECK32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
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; CHECK32-NEXT: andl $1, %ecx
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; CHECK32-NEXT: kmovw %ecx, %k1
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; CHECK32-NEXT: vmovups %zmm0, (%eax) {%k1}
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; CHECK32-NEXT: vzeroupper
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; CHECK32-NEXT: retl
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entry:
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%0 = bitcast float* %__W to <16 x float>*
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%shuffle.i.i = shufflevector <4 x float> %__A, <4 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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@ -80,11 +130,22 @@ entry:
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}
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define void @test_mm_mask_store_sd(double* %__W, i8 zeroext %__U, <2 x double> %__A) local_unnamed_addr #1 {
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; CHECK-LABEL: test_mm_mask_store_sd:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %esi, %k1
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; CHECK-NEXT: vmovsd %xmm0, (%rdi) {%k1}
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; CHECK-NEXT: retq
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; CHECK64-LABEL: test_mm_mask_store_sd:
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; CHECK64: # BB#0: # %entry
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; CHECK64-NEXT: kmovw %esi, %k1
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; CHECK64-NEXT: vmovsd %xmm0, (%rdi) {%k1}
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; CHECK64-NEXT: retq
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;
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; CHECK32-LABEL: test_mm_mask_store_sd:
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; CHECK32: # BB#0: # %entry
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; CHECK32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; CHECK32-NEXT: andb $1, %cl
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; CHECK32-NEXT: kmovw %ecx, %k1
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; CHECK32-NEXT: vmovupd %zmm0, (%eax) {%k1}
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; CHECK32-NEXT: vzeroupper
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; CHECK32-NEXT: retl
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entry:
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%0 = bitcast double* %__W to <8 x double>*
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%shuffle.i.i = shufflevector <2 x double> %__A, <2 x double> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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@ -95,11 +156,24 @@ entry:
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}
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define <4 x float> @test_mm_mask_load_ss(<4 x float> %__A, i8 zeroext %__U, float* %__W) local_unnamed_addr #2 {
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; CHECK-LABEL: test_mm_mask_load_ss:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovss (%rsi), %xmm0 {%k1}
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; CHECK-NEXT: retq
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; CHECK64-LABEL: test_mm_mask_load_ss:
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; CHECK64: # BB#0: # %entry
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; CHECK64-NEXT: kmovw %edi, %k1
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; CHECK64-NEXT: vmovss (%rsi), %xmm0 {%k1}
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; CHECK64-NEXT: retq
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;
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; CHECK32-LABEL: test_mm_mask_load_ss:
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; CHECK32: # BB#0: # %entry
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
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; CHECK32-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; CHECK32-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; CHECK32-NEXT: andl $1, %ecx
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; CHECK32-NEXT: kmovw %ecx, %k1
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; CHECK32-NEXT: vmovups (%eax), %zmm0 {%k1}
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; CHECK32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
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; CHECK32-NEXT: vzeroupper
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; CHECK32-NEXT: retl
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entry:
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%shuffle.i = shufflevector <4 x float> %__A, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 4>
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%0 = bitcast float* %__W to <16 x float>*
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@ -113,11 +187,23 @@ entry:
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}
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define <2 x double> @test_mm_mask_load_sd(<2 x double> %__A, i8 zeroext %__U, double* %__W) local_unnamed_addr #2 {
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; CHECK-LABEL: test_mm_mask_load_sd:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovsd (%rsi), %xmm0 {%k1}
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; CHECK-NEXT: retq
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; CHECK64-LABEL: test_mm_mask_load_sd:
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; CHECK64: # BB#0: # %entry
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; CHECK64-NEXT: kmovw %edi, %k1
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; CHECK64-NEXT: vmovsd (%rsi), %xmm0 {%k1}
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; CHECK64-NEXT: retq
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;
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; CHECK32-LABEL: test_mm_mask_load_sd:
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; CHECK32: # BB#0: # %entry
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; CHECK32-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
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; CHECK32-NEXT: andb $1, %cl
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; CHECK32-NEXT: kmovw %ecx, %k1
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; CHECK32-NEXT: vmovupd (%eax), %zmm0 {%k1}
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; CHECK32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
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; CHECK32-NEXT: vzeroupper
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; CHECK32-NEXT: retl
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entry:
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%shuffle5.i = insertelement <2 x double> %__A, double 0.000000e+00, i32 1
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%0 = bitcast double* %__W to <8 x double>*
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@ -130,11 +216,22 @@ entry:
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}
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define <4 x float> @test_mm_maskz_load_ss(i8 zeroext %__U, float* %__W) local_unnamed_addr #2 {
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; CHECK-LABEL: test_mm_maskz_load_ss:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovss (%rsi), %xmm0 {%k1} {z}
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; CHECK-NEXT: retq
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; CHECK64-LABEL: test_mm_maskz_load_ss:
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; CHECK64: # BB#0: # %entry
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; CHECK64-NEXT: kmovw %edi, %k1
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; CHECK64-NEXT: vmovss (%rsi), %xmm0 {%k1} {z}
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; CHECK64-NEXT: retq
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;
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; CHECK32-LABEL: test_mm_maskz_load_ss:
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; CHECK32: # BB#0: # %entry
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
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; CHECK32-NEXT: andl $1, %ecx
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; CHECK32-NEXT: kmovw %ecx, %k1
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; CHECK32-NEXT: vmovups (%eax), %zmm0 {%k1} {z}
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; CHECK32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
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; CHECK32-NEXT: vzeroupper
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; CHECK32-NEXT: retl
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entry:
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%0 = bitcast float* %__W to <16 x float>*
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%1 = and i8 %__U, 1
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@ -146,11 +243,22 @@ entry:
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}
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define <2 x double> @test_mm_maskz_load_sd(i8 zeroext %__U, double* %__W) local_unnamed_addr #2 {
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; CHECK-LABEL: test_mm_maskz_load_sd:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovsd (%rsi), %xmm0 {%k1} {z}
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; CHECK-NEXT: retq
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; CHECK64-LABEL: test_mm_maskz_load_sd:
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; CHECK64: # BB#0: # %entry
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; CHECK64-NEXT: kmovw %edi, %k1
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; CHECK64-NEXT: vmovsd (%rsi), %xmm0 {%k1} {z}
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; CHECK64-NEXT: retq
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;
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; CHECK32-LABEL: test_mm_maskz_load_sd:
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; CHECK32: # BB#0: # %entry
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; CHECK32-NEXT: andb $1, %cl
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; CHECK32-NEXT: kmovw %ecx, %k1
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; CHECK32-NEXT: vmovupd (%eax), %zmm0 {%k1} {z}
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; CHECK32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
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; CHECK32-NEXT: vzeroupper
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; CHECK32-NEXT: retl
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entry:
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%0 = bitcast double* %__W to <8 x double>*
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%1 = and i8 %__U, 1
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