[MIPS GlobalISel] Select floating point arithmetic operations
Select 32 and 64 bit floating point add, sub, mul and div for MIPS32. Differential Revision: https://reviews.llvm.org/D60191 llvm-svn: 357584
This commit is contained in:
Petar Avramovic
parent
5820db93c9
commit
afa3afa384
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@ -81,9 +81,6 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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.legalFor({s32})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder(G_FCONSTANT)
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.legalFor({s32, s64});
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getActionDefinitionsBuilder(G_GEP)
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.legalFor({{p0, s32}});
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@ -93,6 +90,13 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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getActionDefinitionsBuilder(G_GLOBAL_VALUE)
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.legalFor({p0});
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// FP instructions
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getActionDefinitionsBuilder(G_FCONSTANT)
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.legalFor({s32, s64});
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getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
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.legalFor({s32, s64});
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computeTables();
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verify(*ST.getInstrInfo());
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}
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@ -81,6 +81,7 @@ const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass(
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case Mips::SP32RegClassID:
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return getRegBank(Mips::GPRBRegBankID);
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case Mips::FGRCCRegClassID:
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case Mips::FGR32RegClassID:
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case Mips::FGR64RegClassID:
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case Mips::AFGR64RegClassID:
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return getRegBank(Mips::FPRBRegBankID);
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@ -128,9 +129,19 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case G_UREM:
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OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
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break;
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case G_FADD:
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case G_FSUB:
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case G_FMUL:
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case G_FDIV: {
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unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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assert((Size == 32 || Size == 64) && "Unsupported floating point size");
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OperandsMapping = Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
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: &Mips::ValueMappings[Mips::DPRIdx];
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break;
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}
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case G_FCONSTANT: {
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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unsigned Size = Ty.getSizeInBits();
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unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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assert((Size == 32 || Size == 64) && "Unsupported floating point size");
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const RegisterBankInfo::ValueMapping *FPRValueMapping =
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Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
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: &Mips::ValueMappings[Mips::DPRIdx];
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@ -0,0 +1,263 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
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--- |
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define void @float_add() {entry: ret void}
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define void @float_sub() {entry: ret void}
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define void @float_mul() {entry: ret void}
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define void @float_div() {entry: ret void}
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define void @double_add() {entry: ret void}
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define void @double_sub() {entry: ret void}
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define void @double_mul() {entry: ret void}
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define void @double_div() {entry: ret void}
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...
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---
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name: float_add
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12, $f14
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; FP32-LABEL: name: float_add
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; FP32: liveins: $f12, $f14
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; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP32: [[FADD_S:%[0-9]+]]:fgr32 = FADD_S [[COPY]], [[COPY1]]
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; FP32: $f0 = COPY [[FADD_S]]
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: float_add
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; FP64: liveins: $f12, $f14
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; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP64: [[FADD_S:%[0-9]+]]:fgr32 = FADD_S [[COPY]], [[COPY1]]
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; FP64: $f0 = COPY [[FADD_S]]
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; FP64: RetRA implicit $f0
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%0:fprb(s32) = COPY $f12
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%1:fprb(s32) = COPY $f14
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%2:fprb(s32) = G_FADD %0, %1
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$f0 = COPY %2(s32)
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RetRA implicit $f0
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...
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---
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name: float_sub
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12, $f14
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; FP32-LABEL: name: float_sub
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; FP32: liveins: $f12, $f14
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; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP32: [[FSUB_S:%[0-9]+]]:fgr32 = FSUB_S [[COPY]], [[COPY1]]
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; FP32: $f0 = COPY [[FSUB_S]]
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: float_sub
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; FP64: liveins: $f12, $f14
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; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP64: [[FSUB_S:%[0-9]+]]:fgr32 = FSUB_S [[COPY]], [[COPY1]]
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; FP64: $f0 = COPY [[FSUB_S]]
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; FP64: RetRA implicit $f0
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%0:fprb(s32) = COPY $f12
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%1:fprb(s32) = COPY $f14
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%2:fprb(s32) = G_FSUB %0, %1
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$f0 = COPY %2(s32)
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RetRA implicit $f0
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...
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---
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name: float_mul
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12, $f14
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; FP32-LABEL: name: float_mul
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; FP32: liveins: $f12, $f14
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; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP32: [[FMUL_S:%[0-9]+]]:fgr32 = FMUL_S [[COPY]], [[COPY1]]
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; FP32: $f0 = COPY [[FMUL_S]]
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: float_mul
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; FP64: liveins: $f12, $f14
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; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP64: [[FMUL_S:%[0-9]+]]:fgr32 = FMUL_S [[COPY]], [[COPY1]]
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; FP64: $f0 = COPY [[FMUL_S]]
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; FP64: RetRA implicit $f0
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%0:fprb(s32) = COPY $f12
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%1:fprb(s32) = COPY $f14
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%2:fprb(s32) = G_FMUL %0, %1
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$f0 = COPY %2(s32)
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RetRA implicit $f0
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...
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---
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name: float_div
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12, $f14
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; FP32-LABEL: name: float_div
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; FP32: liveins: $f12, $f14
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; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP32: [[FDIV_S:%[0-9]+]]:fgr32 = FDIV_S [[COPY]], [[COPY1]]
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; FP32: $f0 = COPY [[FDIV_S]]
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: float_div
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; FP64: liveins: $f12, $f14
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; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP64: [[FDIV_S:%[0-9]+]]:fgr32 = FDIV_S [[COPY]], [[COPY1]]
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; FP64: $f0 = COPY [[FDIV_S]]
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; FP64: RetRA implicit $f0
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%0:fprb(s32) = COPY $f12
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%1:fprb(s32) = COPY $f14
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%2:fprb(s32) = G_FDIV %0, %1
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$f0 = COPY %2(s32)
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RetRA implicit $f0
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...
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---
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name: double_add
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d6, $d7
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; FP32-LABEL: name: double_add
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; FP32: liveins: $d6, $d7
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; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
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; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
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; FP32: [[FADD_D32_:%[0-9]+]]:afgr64 = FADD_D32 [[COPY]], [[COPY1]]
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; FP32: $d0 = COPY [[FADD_D32_]]
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; FP32: RetRA implicit $d0
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; FP64-LABEL: name: double_add
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; FP64: liveins: $d6, $d7
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; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
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; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
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; FP64: [[FADD_D64_:%[0-9]+]]:fgr64 = FADD_D64 [[COPY]], [[COPY1]]
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; FP64: $d0 = COPY [[FADD_D64_]]
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; FP64: RetRA implicit $d0
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%0:fprb(s64) = COPY $d6
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%1:fprb(s64) = COPY $d7
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%2:fprb(s64) = G_FADD %0, %1
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$d0 = COPY %2(s64)
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RetRA implicit $d0
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...
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---
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name: double_sub
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d6, $d7
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; FP32-LABEL: name: double_sub
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; FP32: liveins: $d6, $d7
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; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
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; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
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; FP32: [[FSUB_D32_:%[0-9]+]]:afgr64 = FSUB_D32 [[COPY]], [[COPY1]]
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; FP32: $d0 = COPY [[FSUB_D32_]]
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; FP32: RetRA implicit $d0
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; FP64-LABEL: name: double_sub
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; FP64: liveins: $d6, $d7
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; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
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; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
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; FP64: [[FSUB_D64_:%[0-9]+]]:fgr64 = FSUB_D64 [[COPY]], [[COPY1]]
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; FP64: $d0 = COPY [[FSUB_D64_]]
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; FP64: RetRA implicit $d0
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%0:fprb(s64) = COPY $d6
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%1:fprb(s64) = COPY $d7
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%2:fprb(s64) = G_FSUB %0, %1
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$d0 = COPY %2(s64)
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RetRA implicit $d0
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...
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---
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name: double_mul
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d6, $d7
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; FP32-LABEL: name: double_mul
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; FP32: liveins: $d6, $d7
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; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
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; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
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; FP32: [[FMUL_D32_:%[0-9]+]]:afgr64 = FMUL_D32 [[COPY]], [[COPY1]]
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; FP32: $d0 = COPY [[FMUL_D32_]]
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; FP32: RetRA implicit $d0
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; FP64-LABEL: name: double_mul
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; FP64: liveins: $d6, $d7
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; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
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; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
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; FP64: [[FMUL_D64_:%[0-9]+]]:fgr64 = FMUL_D64 [[COPY]], [[COPY1]]
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; FP64: $d0 = COPY [[FMUL_D64_]]
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; FP64: RetRA implicit $d0
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%0:fprb(s64) = COPY $d6
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%1:fprb(s64) = COPY $d7
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%2:fprb(s64) = G_FMUL %0, %1
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$d0 = COPY %2(s64)
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RetRA implicit $d0
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...
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---
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name: double_div
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d6, $d7
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; FP32-LABEL: name: double_div
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; FP32: liveins: $d6, $d7
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; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
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; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
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; FP32: [[FDIV_D32_:%[0-9]+]]:afgr64 = FDIV_D32 [[COPY]], [[COPY1]]
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; FP32: $d0 = COPY [[FDIV_D32_]]
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; FP32: RetRA implicit $d0
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; FP64-LABEL: name: double_div
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; FP64: liveins: $d6, $d7
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; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
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; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
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; FP64: [[FDIV_D64_:%[0-9]+]]:fgr64 = FDIV_D64 [[COPY]], [[COPY1]]
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; FP64: $d0 = COPY [[FDIV_D64_]]
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; FP64: RetRA implicit $d0
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%0:fprb(s64) = COPY $d6
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%1:fprb(s64) = COPY $d7
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%2:fprb(s64) = G_FDIV %0, %1
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$d0 = COPY %2(s64)
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RetRA implicit $d0
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...
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@ -0,0 +1,248 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
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--- |
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define void @float_add() {entry: ret void}
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define void @float_sub() {entry: ret void}
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define void @float_mul() {entry: ret void}
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define void @float_div() {entry: ret void}
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define void @double_add() {entry: ret void}
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define void @double_sub() {entry: ret void}
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define void @double_mul() {entry: ret void}
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define void @double_div() {entry: ret void}
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...
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---
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name: float_add
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12, $f14
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; FP32-LABEL: name: float_add
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; FP32: liveins: $f12, $f14
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
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; FP32: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
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; FP32: $f0 = COPY [[FADD]](s32)
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: float_add
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; FP64: liveins: $f12, $f14
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
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; FP64: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
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; FP64: $f0 = COPY [[FADD]](s32)
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; FP64: RetRA implicit $f0
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%0:_(s32) = COPY $f12
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%1:_(s32) = COPY $f14
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%2:_(s32) = G_FADD %0, %1
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$f0 = COPY %2(s32)
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RetRA implicit $f0
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...
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---
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name: float_sub
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12, $f14
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; FP32-LABEL: name: float_sub
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; FP32: liveins: $f12, $f14
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
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; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
|
||||
; FP32: $f0 = COPY [[FSUB]](s32)
|
||||
; FP32: RetRA implicit $f0
|
||||
; FP64-LABEL: name: float_sub
|
||||
; FP64: liveins: $f12, $f14
|
||||
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
|
||||
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
|
||||
; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
|
||||
; FP64: $f0 = COPY [[FSUB]](s32)
|
||||
; FP64: RetRA implicit $f0
|
||||
%0:_(s32) = COPY $f12
|
||||
%1:_(s32) = COPY $f14
|
||||
%2:_(s32) = G_FSUB %0, %1
|
||||
$f0 = COPY %2(s32)
|
||||
RetRA implicit $f0
|
||||
|
||||
...
|
||||
---
|
||||
name: float_mul
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12, $f14
|
||||
|
||||
; FP32-LABEL: name: float_mul
|
||||
; FP32: liveins: $f12, $f14
|
||||
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
|
||||
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
|
||||
; FP32: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
|
||||
; FP32: $f0 = COPY [[FMUL]](s32)
|
||||
; FP32: RetRA implicit $f0
|
||||
; FP64-LABEL: name: float_mul
|
||||
; FP64: liveins: $f12, $f14
|
||||
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
|
||||
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
|
||||
; FP64: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
|
||||
; FP64: $f0 = COPY [[FMUL]](s32)
|
||||
; FP64: RetRA implicit $f0
|
||||
%0:_(s32) = COPY $f12
|
||||
%1:_(s32) = COPY $f14
|
||||
%2:_(s32) = G_FMUL %0, %1
|
||||
$f0 = COPY %2(s32)
|
||||
RetRA implicit $f0
|
||||
|
||||
...
|
||||
---
|
||||
name: float_div
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12, $f14
|
||||
|
||||
; FP32-LABEL: name: float_div
|
||||
; FP32: liveins: $f12, $f14
|
||||
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
|
||||
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
|
||||
; FP32: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[COPY]], [[COPY1]]
|
||||
; FP32: $f0 = COPY [[FDIV]](s32)
|
||||
; FP32: RetRA implicit $f0
|
||||
; FP64-LABEL: name: float_div
|
||||
; FP64: liveins: $f12, $f14
|
||||
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
|
||||
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
|
||||
; FP64: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[COPY]], [[COPY1]]
|
||||
; FP64: $f0 = COPY [[FDIV]](s32)
|
||||
; FP64: RetRA implicit $f0
|
||||
%0:_(s32) = COPY $f12
|
||||
%1:_(s32) = COPY $f14
|
||||
%2:_(s32) = G_FDIV %0, %1
|
||||
$f0 = COPY %2(s32)
|
||||
RetRA implicit $f0
|
||||
|
||||
...
|
||||
---
|
||||
name: double_add
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $d6, $d7
|
||||
|
||||
; FP32-LABEL: name: double_add
|
||||
; FP32: liveins: $d6, $d7
|
||||
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
|
||||
; FP32: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]]
|
||||
; FP32: $d0 = COPY [[FADD]](s64)
|
||||
; FP32: RetRA implicit $d0
|
||||
; FP64-LABEL: name: double_add
|
||||
; FP64: liveins: $d6, $d7
|
||||
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
|
||||
; FP64: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]]
|
||||
; FP64: $d0 = COPY [[FADD]](s64)
|
||||
; FP64: RetRA implicit $d0
|
||||
%0:_(s64) = COPY $d6
|
||||
%1:_(s64) = COPY $d7
|
||||
%2:_(s64) = G_FADD %0, %1
|
||||
$d0 = COPY %2(s64)
|
||||
RetRA implicit $d0
|
||||
|
||||
...
|
||||
---
|
||||
name: double_sub
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $d6, $d7
|
||||
|
||||
; FP32-LABEL: name: double_sub
|
||||
; FP32: liveins: $d6, $d7
|
||||
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
|
||||
; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[COPY1]]
|
||||
; FP32: $d0 = COPY [[FSUB]](s64)
|
||||
; FP32: RetRA implicit $d0
|
||||
; FP64-LABEL: name: double_sub
|
||||
; FP64: liveins: $d6, $d7
|
||||
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
|
||||
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[COPY1]]
|
||||
; FP64: $d0 = COPY [[FSUB]](s64)
|
||||
; FP64: RetRA implicit $d0
|
||||
%0:_(s64) = COPY $d6
|
||||
%1:_(s64) = COPY $d7
|
||||
%2:_(s64) = G_FSUB %0, %1
|
||||
$d0 = COPY %2(s64)
|
||||
RetRA implicit $d0
|
||||
|
||||
...
|
||||
---
|
||||
name: double_mul
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $d6, $d7
|
||||
|
||||
; FP32-LABEL: name: double_mul
|
||||
; FP32: liveins: $d6, $d7
|
||||
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
|
||||
; FP32: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
|
||||
; FP32: $d0 = COPY [[FMUL]](s64)
|
||||
; FP32: RetRA implicit $d0
|
||||
; FP64-LABEL: name: double_mul
|
||||
; FP64: liveins: $d6, $d7
|
||||
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
|
||||
; FP64: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
|
||||
; FP64: $d0 = COPY [[FMUL]](s64)
|
||||
; FP64: RetRA implicit $d0
|
||||
%0:_(s64) = COPY $d6
|
||||
%1:_(s64) = COPY $d7
|
||||
%2:_(s64) = G_FMUL %0, %1
|
||||
$d0 = COPY %2(s64)
|
||||
RetRA implicit $d0
|
||||
|
||||
...
|
||||
---
|
||||
name: double_div
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $d6, $d7
|
||||
|
||||
; FP32-LABEL: name: double_div
|
||||
; FP32: liveins: $d6, $d7
|
||||
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
|
||||
; FP32: [[FDIV:%[0-9]+]]:_(s64) = G_FDIV [[COPY]], [[COPY1]]
|
||||
; FP32: $d0 = COPY [[FDIV]](s64)
|
||||
; FP32: RetRA implicit $d0
|
||||
; FP64-LABEL: name: double_div
|
||||
; FP64: liveins: $d6, $d7
|
||||
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
|
||||
; FP64: [[FDIV:%[0-9]+]]:_(s64) = G_FDIV [[COPY]], [[COPY1]]
|
||||
; FP64: $d0 = COPY [[FDIV]](s64)
|
||||
; FP64: RetRA implicit $d0
|
||||
%0:_(s64) = COPY $d6
|
||||
%1:_(s64) = COPY $d7
|
||||
%2:_(s64) = G_FDIV %0, %1
|
||||
$d0 = COPY %2(s64)
|
||||
RetRA implicit $d0
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
|
||||
|
||||
define float @float_add(float %a, float %b) {
|
||||
; MIPS32-LABEL: float_add:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: add.s $f0, $f12, $f14
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%add = fadd float %a, %b
|
||||
ret float %add
|
||||
}
|
||||
|
||||
define float @float_sub(float %a, float %b) {
|
||||
; MIPS32-LABEL: float_sub:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: sub.s $f0, $f12, $f14
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%sub = fsub float %a, %b
|
||||
ret float %sub
|
||||
}
|
||||
|
||||
define float @float_mul(float %a, float %b) {
|
||||
; MIPS32-LABEL: float_mul:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: mul.s $f0, $f12, $f14
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%mul = fmul float %a, %b
|
||||
ret float %mul
|
||||
}
|
||||
|
||||
define float @float_div(float %a, float %b) {
|
||||
; MIPS32-LABEL: float_div:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: div.s $f0, $f12, $f14
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%div = fdiv float %a, %b
|
||||
ret float %div
|
||||
}
|
||||
|
||||
define double @double_add(double %a, double %b) {
|
||||
; MIPS32-LABEL: double_add:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: add.d $f0, $f12, $f14
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%add = fadd double %a, %b
|
||||
ret double %add
|
||||
}
|
||||
|
||||
define double @double_sub(double %a, double %b) {
|
||||
; MIPS32-LABEL: double_sub:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: sub.d $f0, $f12, $f14
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%sub = fsub double %a, %b
|
||||
ret double %sub
|
||||
}
|
||||
|
||||
define double @double_mul(double %a, double %b) {
|
||||
; MIPS32-LABEL: double_mul:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: mul.d $f0, $f12, $f14
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%mul = fmul double %a, %b
|
||||
ret double %mul
|
||||
}
|
||||
|
||||
define double @double_div(double %a, double %b) {
|
||||
; MIPS32-LABEL: double_div:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: div.d $f0, $f12, $f14
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%div = fdiv double %a, %b
|
||||
ret double %div
|
||||
}
|
||||
|
|
@ -0,0 +1,256 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
|
||||
|
||||
--- |
|
||||
|
||||
define void @float_add() {entry: ret void}
|
||||
define void @float_sub() {entry: ret void}
|
||||
define void @float_mul() {entry: ret void}
|
||||
define void @float_div() {entry: ret void}
|
||||
define void @double_add() {entry: ret void}
|
||||
define void @double_sub() {entry: ret void}
|
||||
define void @double_mul() {entry: ret void}
|
||||
define void @double_div() {entry: ret void}
|
||||
|
||||
...
|
||||
---
|
||||
name: float_add
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12, $f14
|
||||
|
||||
; FP32-LABEL: name: float_add
|
||||
; FP32: liveins: $f12, $f14
|
||||
; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
|
||||
; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
|
||||
; FP32: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY]], [[COPY1]]
|
||||
; FP32: $f0 = COPY [[FADD]](s32)
|
||||
; FP32: RetRA implicit $f0
|
||||
; FP64-LABEL: name: float_add
|
||||
; FP64: liveins: $f12, $f14
|
||||
; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
|
||||
; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
|
||||
; FP64: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY]], [[COPY1]]
|
||||
; FP64: $f0 = COPY [[FADD]](s32)
|
||||
; FP64: RetRA implicit $f0
|
||||
%0:_(s32) = COPY $f12
|
||||
%1:_(s32) = COPY $f14
|
||||
%2:_(s32) = G_FADD %0, %1
|
||||
$f0 = COPY %2(s32)
|
||||
RetRA implicit $f0
|
||||
|
||||
...
|
||||
---
|
||||
name: float_sub
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12, $f14
|
||||
|
||||
; FP32-LABEL: name: float_sub
|
||||
; FP32: liveins: $f12, $f14
|
||||
; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
|
||||
; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
|
||||
; FP32: [[FSUB:%[0-9]+]]:fprb(s32) = G_FSUB [[COPY]], [[COPY1]]
|
||||
; FP32: $f0 = COPY [[FSUB]](s32)
|
||||
; FP32: RetRA implicit $f0
|
||||
; FP64-LABEL: name: float_sub
|
||||
; FP64: liveins: $f12, $f14
|
||||
; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
|
||||
; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
|
||||
; FP64: [[FSUB:%[0-9]+]]:fprb(s32) = G_FSUB [[COPY]], [[COPY1]]
|
||||
; FP64: $f0 = COPY [[FSUB]](s32)
|
||||
; FP64: RetRA implicit $f0
|
||||
%0:_(s32) = COPY $f12
|
||||
%1:_(s32) = COPY $f14
|
||||
%2:_(s32) = G_FSUB %0, %1
|
||||
$f0 = COPY %2(s32)
|
||||
RetRA implicit $f0
|
||||
|
||||
...
|
||||
---
|
||||
name: float_mul
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12, $f14
|
||||
|
||||
; FP32-LABEL: name: float_mul
|
||||
; FP32: liveins: $f12, $f14
|
||||
; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
|
||||
; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
|
||||
; FP32: [[FMUL:%[0-9]+]]:fprb(s32) = G_FMUL [[COPY]], [[COPY1]]
|
||||
; FP32: $f0 = COPY [[FMUL]](s32)
|
||||
; FP32: RetRA implicit $f0
|
||||
; FP64-LABEL: name: float_mul
|
||||
; FP64: liveins: $f12, $f14
|
||||
; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
|
||||
; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
|
||||
; FP64: [[FMUL:%[0-9]+]]:fprb(s32) = G_FMUL [[COPY]], [[COPY1]]
|
||||
; FP64: $f0 = COPY [[FMUL]](s32)
|
||||
; FP64: RetRA implicit $f0
|
||||
%0:_(s32) = COPY $f12
|
||||
%1:_(s32) = COPY $f14
|
||||
%2:_(s32) = G_FMUL %0, %1
|
||||
$f0 = COPY %2(s32)
|
||||
RetRA implicit $f0
|
||||
|
||||
...
|
||||
---
|
||||
name: float_div
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12, $f14
|
||||
|
||||
; FP32-LABEL: name: float_div
|
||||
; FP32: liveins: $f12, $f14
|
||||
; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
|
||||
; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
|
||||
; FP32: [[FDIV:%[0-9]+]]:fprb(s32) = G_FDIV [[COPY]], [[COPY1]]
|
||||
; FP32: $f0 = COPY [[FDIV]](s32)
|
||||
; FP32: RetRA implicit $f0
|
||||
; FP64-LABEL: name: float_div
|
||||
; FP64: liveins: $f12, $f14
|
||||
; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
|
||||
; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
|
||||
; FP64: [[FDIV:%[0-9]+]]:fprb(s32) = G_FDIV [[COPY]], [[COPY1]]
|
||||
; FP64: $f0 = COPY [[FDIV]](s32)
|
||||
; FP64: RetRA implicit $f0
|
||||
%0:_(s32) = COPY $f12
|
||||
%1:_(s32) = COPY $f14
|
||||
%2:_(s32) = G_FDIV %0, %1
|
||||
$f0 = COPY %2(s32)
|
||||
RetRA implicit $f0
|
||||
|
||||
...
|
||||
---
|
||||
name: double_add
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $d6, $d7
|
||||
|
||||
; FP32-LABEL: name: double_add
|
||||
; FP32: liveins: $d6, $d7
|
||||
; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
|
||||
; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
|
||||
; FP32: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY]], [[COPY1]]
|
||||
; FP32: $d0 = COPY [[FADD]](s64)
|
||||
; FP32: RetRA implicit $d0
|
||||
; FP64-LABEL: name: double_add
|
||||
; FP64: liveins: $d6, $d7
|
||||
; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
|
||||
; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
|
||||
; FP64: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY]], [[COPY1]]
|
||||
; FP64: $d0 = COPY [[FADD]](s64)
|
||||
; FP64: RetRA implicit $d0
|
||||
%0:_(s64) = COPY $d6
|
||||
%1:_(s64) = COPY $d7
|
||||
%2:_(s64) = G_FADD %0, %1
|
||||
$d0 = COPY %2(s64)
|
||||
RetRA implicit $d0
|
||||
|
||||
...
|
||||
---
|
||||
name: double_sub
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $d6, $d7
|
||||
|
||||
; FP32-LABEL: name: double_sub
|
||||
; FP32: liveins: $d6, $d7
|
||||
; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
|
||||
; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
|
||||
; FP32: [[FSUB:%[0-9]+]]:fprb(s64) = G_FSUB [[COPY]], [[COPY1]]
|
||||
; FP32: $d0 = COPY [[FSUB]](s64)
|
||||
; FP32: RetRA implicit $d0
|
||||
; FP64-LABEL: name: double_sub
|
||||
; FP64: liveins: $d6, $d7
|
||||
; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
|
||||
; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
|
||||
; FP64: [[FSUB:%[0-9]+]]:fprb(s64) = G_FSUB [[COPY]], [[COPY1]]
|
||||
; FP64: $d0 = COPY [[FSUB]](s64)
|
||||
; FP64: RetRA implicit $d0
|
||||
%0:_(s64) = COPY $d6
|
||||
%1:_(s64) = COPY $d7
|
||||
%2:_(s64) = G_FSUB %0, %1
|
||||
$d0 = COPY %2(s64)
|
||||
RetRA implicit $d0
|
||||
|
||||
...
|
||||
---
|
||||
name: double_mul
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $d6, $d7
|
||||
|
||||
; FP32-LABEL: name: double_mul
|
||||
; FP32: liveins: $d6, $d7
|
||||
; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
|
||||
; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
|
||||
; FP32: [[FMUL:%[0-9]+]]:fprb(s64) = G_FMUL [[COPY]], [[COPY1]]
|
||||
; FP32: $d0 = COPY [[FMUL]](s64)
|
||||
; FP32: RetRA implicit $d0
|
||||
; FP64-LABEL: name: double_mul
|
||||
; FP64: liveins: $d6, $d7
|
||||
; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
|
||||
; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
|
||||
; FP64: [[FMUL:%[0-9]+]]:fprb(s64) = G_FMUL [[COPY]], [[COPY1]]
|
||||
; FP64: $d0 = COPY [[FMUL]](s64)
|
||||
; FP64: RetRA implicit $d0
|
||||
%0:_(s64) = COPY $d6
|
||||
%1:_(s64) = COPY $d7
|
||||
%2:_(s64) = G_FMUL %0, %1
|
||||
$d0 = COPY %2(s64)
|
||||
RetRA implicit $d0
|
||||
|
||||
...
|
||||
---
|
||||
name: double_div
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $d6, $d7
|
||||
|
||||
; FP32-LABEL: name: double_div
|
||||
; FP32: liveins: $d6, $d7
|
||||
; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
|
||||
; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
|
||||
; FP32: [[FDIV:%[0-9]+]]:fprb(s64) = G_FDIV [[COPY]], [[COPY1]]
|
||||
; FP32: $d0 = COPY [[FDIV]](s64)
|
||||
; FP32: RetRA implicit $d0
|
||||
; FP64-LABEL: name: double_div
|
||||
; FP64: liveins: $d6, $d7
|
||||
; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
|
||||
; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
|
||||
; FP64: [[FDIV:%[0-9]+]]:fprb(s64) = G_FDIV [[COPY]], [[COPY1]]
|
||||
; FP64: $d0 = COPY [[FDIV]](s64)
|
||||
; FP64: RetRA implicit $d0
|
||||
%0:_(s64) = COPY $d6
|
||||
%1:_(s64) = COPY $d7
|
||||
%2:_(s64) = G_FDIV %0, %1
|
||||
$d0 = COPY %2(s64)
|
||||
RetRA implicit $d0
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue