[WebAssembly] Codegen for f64x2.convert_low_i32x4_{s,u}
Add a custom DAG combine and ISD opcode for detecting patterns like
(uint_to_fp (extract_subvector ...))
before the extract_subvector is expanded to ensure that they will ultimately
lower to f64x2.convert_low_i32x4_{s,u} instructions. Since these instructions
are no longer prototypes and can now be produced via standard IR, this commit
also removes the target intrinsics and builtins that had been used to prototype
the instructions.
Differential Revision: https://reviews.llvm.org/D100425
This commit is contained in:
Thomas Lively
parent
2fe4909748
commit
af7925b4dd
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@ -196,8 +196,6 @@ TARGET_BUILTIN(__builtin_wasm_extend_high_s_i32x4_i64x2, "V2LLiV4i", "nc", "simd
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TARGET_BUILTIN(__builtin_wasm_extend_low_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_extend_high_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_convert_low_s_i32x4_f64x2, "V2dV4i", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_convert_low_u_i32x4_f64x2, "V2dV4Ui", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_trunc_sat_zero_s_f64x2_i32x4, "V4iV2d", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4, "V4UiV2d", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_demote_zero_f64x2_f32x4, "V4fV2d", "nc", "simd128")
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@ -17500,23 +17500,6 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
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Function *Callee = CGM.getIntrinsic(IntNo);
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return Builder.CreateCall(Callee, Vec);
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}
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case WebAssembly::BI__builtin_wasm_convert_low_s_i32x4_f64x2:
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case WebAssembly::BI__builtin_wasm_convert_low_u_i32x4_f64x2: {
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Value *Vec = EmitScalarExpr(E->getArg(0));
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unsigned IntNo;
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switch (BuiltinID) {
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case WebAssembly::BI__builtin_wasm_convert_low_s_i32x4_f64x2:
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IntNo = Intrinsic::wasm_convert_low_signed;
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break;
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case WebAssembly::BI__builtin_wasm_convert_low_u_i32x4_f64x2:
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IntNo = Intrinsic::wasm_convert_low_unsigned;
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break;
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default:
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llvm_unreachable("unexpected builtin ID");
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}
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Function *Callee = CGM.getIntrinsic(IntNo);
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return Builder.CreateCall(Callee, Vec);
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}
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case WebAssembly::BI__builtin_wasm_trunc_sat_zero_s_f64x2_i32x4:
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case WebAssembly::BI__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4: {
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Value *Vec = EmitScalarExpr(E->getArg(0));
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@ -914,18 +914,6 @@ u64x2 extend_high_u_i32x4_i64x2(u32x4 x) {
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// WEBASSEMBLY: ret
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}
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f64x2 convert_low_s_i32x4_f64x2(i32x4 x) {
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return __builtin_wasm_convert_low_s_i32x4_f64x2(x);
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// WEBASSEMBLY: call <2 x double> @llvm.wasm.convert.low.signed(<4 x i32> %x)
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// WEBASSEMBLY: ret
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}
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f64x2 convert_low_u_i32x4_f64x2(u32x4 x) {
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return __builtin_wasm_convert_low_u_i32x4_f64x2(x);
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// WEBASSEMBLY: call <2 x double> @llvm.wasm.convert.low.unsigned(<4 x i32> %x)
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// WEBASSEMBLY: ret
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}
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i32x4 trunc_sat_zero_s_f64x2_i32x4(f64x2 x) {
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return __builtin_wasm_trunc_sat_zero_s_f64x2_i32x4(x);
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// WEBASSEMBLY: call <4 x i32> @llvm.wasm.trunc.sat.zero.signed(<2 x double> %x)
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@ -275,12 +275,6 @@ def int_wasm_extadd_pairwise_unsigned :
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[IntrNoMem, IntrSpeculatable]>;
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// TODO: Remove these if possible if they are merged to the spec.
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def int_wasm_convert_low_signed :
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Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_convert_low_unsigned :
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Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_trunc_sat_zero_signed :
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Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty],
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[IntrNoMem, IntrSpeculatable]>;
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@ -33,6 +33,8 @@ HANDLE_NODETYPE(EXTEND_LOW_S)
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HANDLE_NODETYPE(EXTEND_LOW_U)
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HANDLE_NODETYPE(EXTEND_HIGH_S)
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HANDLE_NODETYPE(EXTEND_HIGH_U)
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HANDLE_NODETYPE(CONVERT_LOW_S)
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HANDLE_NODETYPE(CONVERT_LOW_U)
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HANDLE_NODETYPE(THROW)
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HANDLE_NODETYPE(CATCH)
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HANDLE_NODETYPE(MEMORY_COPY)
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@ -130,6 +130,10 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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setTargetDAGCombine(ISD::SIGN_EXTEND);
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setTargetDAGCombine(ISD::ZERO_EXTEND);
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// Combine {s,u}int_to_fp of extract_vectors into conversion ops
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setTargetDAGCombine(ISD::SINT_TO_FP);
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setTargetDAGCombine(ISD::UINT_TO_FP);
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// Support saturating add for i8x16 and i16x8
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for (auto Op : {ISD::SADDSAT, ISD::UADDSAT})
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for (auto T : {MVT::v16i8, MVT::v8i16})
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@ -2020,6 +2024,40 @@ performVectorExtendCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
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return DAG.getNode(Op, SDLoc(N), ResVT, Source);
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}
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static SDValue
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performVectorConvertLowCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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auto &DAG = DCI.DAG;
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assert(N->getOpcode() == ISD::SINT_TO_FP ||
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N->getOpcode() == ISD::UINT_TO_FP);
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// Combine ({s,u}int_to_fp (extract_subvector ... 0)) to an
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// f64x2.convert_low_i32x4_{s,u} SDNode.
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auto Extract = N->getOperand(0);
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if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR)
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return SDValue();
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auto Source = Extract.getOperand(0);
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auto *IndexNode = dyn_cast<ConstantSDNode>(Extract.getOperand(1));
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if (IndexNode == nullptr)
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return SDValue();
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auto Index = IndexNode->getZExtValue();
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// The types must be correct.
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EVT ResVT = N->getValueType(0);
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if (ResVT != MVT::v2f64 || Extract.getValueType() != MVT::v2i32)
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return SDValue();
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// The extracted vector must be the low half.
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if (Index != 0)
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return SDValue();
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unsigned Op = N->getOpcode() == ISD::SINT_TO_FP
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? WebAssemblyISD::CONVERT_LOW_S
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: WebAssemblyISD::CONVERT_LOW_U;
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return DAG.getNode(Op, SDLoc(N), ResVT, Source);
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}
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SDValue
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WebAssemblyTargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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@ -2031,5 +2069,8 @@ WebAssemblyTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::SIGN_EXTEND:
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case ISD::ZERO_EXTEND:
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return performVectorExtendCombine(N, DCI);
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP:
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return performVectorConvertLowCombine(N, DCI);
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}
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}
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@ -1091,16 +1091,21 @@ multiclass SIMDConvert<Vec vec, Vec arg, SDPatternOperator op, string name,
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defm "" : SIMDConvert<I32x4, F32x4, fp_to_sint, "trunc_sat_f32x4_s", 248>;
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defm "" : SIMDConvert<I32x4, F32x4, fp_to_uint, "trunc_sat_f32x4_u", 249>;
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// Integer to floating point: convert
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defm "" : SIMDConvert<F32x4, I32x4, sint_to_fp, "convert_i32x4_s", 250>;
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defm "" : SIMDConvert<F32x4, I32x4, uint_to_fp, "convert_i32x4_u", 251>;
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// Lower llvm.wasm.trunc.sat.* to saturating instructions
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def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))),
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(fp_to_sint_I32x4 $src)>;
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def : Pat<(v4i32 (int_wasm_trunc_saturate_unsigned (v4f32 V128:$src))),
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(fp_to_uint_I32x4 $src)>;
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// Integer to floating point: convert
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def convert_low_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
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def convert_low_s : SDNode<"WebAssemblyISD::CONVERT_LOW_S", convert_low_t>;
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def convert_low_u : SDNode<"WebAssemblyISD::CONVERT_LOW_U", convert_low_t>;
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defm "" : SIMDConvert<F32x4, I32x4, sint_to_fp, "convert_i32x4_s", 250>;
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defm "" : SIMDConvert<F32x4, I32x4, uint_to_fp, "convert_i32x4_u", 251>;
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defm "" : SIMDConvert<F64x2, I32x4, convert_low_s, "convert_low_i32x4_s", 0xfe>;
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defm "" : SIMDConvert<F64x2, I32x4, convert_low_u, "convert_low_i32x4_u", 0xff>;
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// Extending operations
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def extend_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
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def extend_low_s : SDNode<"WebAssemblyISD::EXTEND_LOW_S", extend_t>;
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@ -1255,10 +1260,6 @@ defm "" : SIMDConvert<I32x4, F64x2, int_wasm_trunc_sat_zero_signed,
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"trunc_sat_zero_f64x2_s", 0xfc>;
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defm "" : SIMDConvert<I32x4, F64x2, int_wasm_trunc_sat_zero_unsigned,
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"trunc_sat_zero_f64x2_u", 0xfd>;
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defm "" : SIMDConvert<F64x2, I32x4, int_wasm_convert_low_signed,
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"convert_low_i32x4_s", 0xfe>;
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defm "" : SIMDConvert<F64x2, I32x4, int_wasm_convert_low_unsigned,
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"convert_low_i32x4_u", 0xff>;
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//===----------------------------------------------------------------------===//
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// Saturating Rounding Q-Format Multiplication
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@ -81,3 +81,25 @@ define <2 x i64> @trunc_sat_u_v2i64(<2 x double> %x) {
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%a = fptoui <2 x double> %x to <2 x i64>
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ret <2 x i64> %a
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}
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; CHECK-LABEL: convert_low_s_v2f64:
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; NO-SIMD128-NOT: f64x2
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; SIMD128-NEXT: .functype convert_low_s_v2f64 (v128) -> (v128){{$}}
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; SIMD128-NEXT: f64x2.convert_low_i32x4_s $push[[R:[0-9]+]]=, $0
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; SIMD128-NEXT: return $pop[[R]]
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define <2 x double> @convert_low_s_v2f64(<4 x i32> %x) {
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%v = shufflevector <4 x i32> %x, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%a = sitofp <2 x i32> %v to <2 x double>
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ret <2 x double> %a
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}
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; CHECK-LABEL: convert_low_u_v2f64:
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; NO-SIMD128-NOT: f64x2
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; SIMD128-NEXT: .functype convert_low_u_v2f64 (v128) -> (v128){{$}}
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; SIMD128-NEXT: f64x2.convert_low_i32x4_u $push[[R:[0-9]+]]=, $0
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; SIMD128-NEXT: return $pop[[R]]
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define <2 x double> @convert_low_u_v2f64(<4 x i32> %x) {
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%v = shufflevector <4 x i32> %x, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%a = uitofp <2 x i32> %v to <2 x double>
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ret <2 x double> %a
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}
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@ -843,26 +843,6 @@ define <2 x double> @nearest_v2f64(<2 x double> %a) {
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ret <2 x double> %v
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}
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; CHECK-LABEL: convert_low_signed_v2f64:
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; CHECK-NEXT: .functype convert_low_signed_v2f64 (v128) -> (v128){{$}}
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; CHECK-NEXT: f64x2.convert_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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declare <2 x double> @llvm.wasm.convert.low.signed(<4 x i32>)
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define <2 x double> @convert_low_signed_v2f64(<4 x i32> %a) {
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%v = call <2 x double> @llvm.wasm.convert.low.signed(<4 x i32> %a)
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ret <2 x double> %v
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}
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; CHECK-LABEL: convert_low_unsigned_v2f64:
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; CHECK-NEXT: .functype convert_low_unsigned_v2f64 (v128) -> (v128){{$}}
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; CHECK-NEXT: f64x2.convert_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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declare <2 x double> @llvm.wasm.convert.low.unsigned(<4 x i32>)
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define <2 x double> @convert_low_unsigned_v2f64(<4 x i32> %a) {
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%v = call <2 x double> @llvm.wasm.convert.low.unsigned(<4 x i32> %a)
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ret <2 x double> %v
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}
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; CHECK-LABEL: promote_low_v2f64:
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; CHECK-NEXT: .functype promote_low_v2f64 (v128) -> (v128){{$}}
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; CHECK-NEXT: f64x2.promote_low_f32x4 $push[[R:[0-9]+]]=, $0{{$}}
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