From af3c79f0acf7ddbc7167d55d302619b6a2078e1b Mon Sep 17 00:00:00 2001 From: Silviu Baranga Date: Thu, 5 Apr 2012 16:19:29 +0000 Subject: [PATCH] Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions. llvm-svn: 154101 --- llvm/lib/Target/ARM/ARMInstrInfo.td | 8 ++++---- .../Disassembler/ARM/unpredictable-ADC-arm.txt | 17 +++++++++++++++++ 2 files changed, 21 insertions(+), 4 deletions(-) create mode 100644 llvm/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index eb30f79eff87..65628544ff1a 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -1331,10 +1331,10 @@ multiclass AI1_adde_sube_irs opcod, string opc, PatFrag opnode, let Inst{4} = 0; let Inst{3-0} = shift{3-0}; } - def rsr : AsI1, + [(set GPRnopc:$Rd, CPSR, (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, Requires<[IsARM]> { bits<4> Rd; bits<4> Rn; @@ -1368,7 +1368,7 @@ multiclass AI1_adde_sube_irs opcod, string opc, PatFrag opnode, cc_out:$s)>, Requires<[IsARM]>; def : InstAlias(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn, + (!cast(!strconcat(baseOpc, "rsr")) GPRnopc:$Rdn, GPRnopc:$Rdn, so_reg_reg:$shift, pred:$p, cc_out:$s)>, Requires<[IsARM]>; diff --git a/llvm/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt b/llvm/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt new file mode 100644 index 000000000000..275bae2fa28e --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x1f 0x12 0xb0 0x00 +0x1f 0x12 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0xf2 0xb0 0x00 +0x13 0xf2 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0x1f 0xb0 0x00 +0x13 0x1f 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0x12 0xbf 0x00 +0x13 0x12 0xbf 0x00