[X86] add mayRaiseFPException flag and FPCW registers for X87 instructions
Summary: This patch adds flag "mayRaiseFPException" , FPCW and FPSW for X87 instructions which could raise float exception. Reviewers: pengfei, RKSimon, andrew.w.kaylor, uweigand, kpn, spatel, cameron.mcinally, craig.topper Reviewed By: craig.topper Subscribers: thakis, hiraditya, llvm-commits Patch by LiuChen. Differential Revision: https://reviews.llvm.org/D68854
This commit is contained in:
Pengfei Wang
parent
cc9e963d65
commit
af3a7de20c
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@ -752,7 +752,7 @@ void mxcsr() {
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__asm fxrstor buf
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}
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// CHECK-LABEL: define void @mxcsr
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// CHECK: call void asm sideeffect inteldialect "fxrstor $0", "=*m,~{dirflag},~{fpsr},~{flags}"
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// CHECK: call void asm sideeffect inteldialect "fxrstor $0", "=*m,~{fpcr},~{dirflag},~{fpsr},~{flags}"
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// Make sure we can find the register for the dirflag for popfd
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void dirflag() {
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@ -282,7 +282,7 @@ def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
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!strconcat("fi", asmstring, "{l}\t$src")>;
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}
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let Defs = [FPSW], Uses = [FPCW] in {
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let Uses = [FPCW], mayRaiseFPException = 1 in {
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// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling
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// resources.
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let hasNoSchedulingInfo = 1 in {
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@ -307,7 +307,7 @@ let SchedRW = [WriteFDivLd] in {
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defm DIV : FPBinary<fdiv, MRM6m, "div">;
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defm DIVR: FPBinary<fdiv, MRM7m, "divr", 0>;
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}
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} // Defs = [FPSW]
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} // Uses = [FPCW], mayRaiseFPException = 1
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class FPST0rInst<Format fp, string asm>
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: FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>;
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@ -319,7 +319,7 @@ class FPrST0PInst<Format fp, string asm>
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// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
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// of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
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// we have to put some 'r's in and take them out of weird places.
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let SchedRW = [WriteFAdd], Defs = [FPSW], Uses = [FPCW] in {
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let SchedRW = [WriteFAdd], Uses = [FPCW], mayRaiseFPException = 1 in {
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def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">;
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def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">;
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def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">;
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@ -330,16 +330,16 @@ def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">;
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def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">;
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def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">;
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} // SchedRW
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let SchedRW = [WriteFCom], Defs = [FPSW], Uses = [FPCW] in {
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let SchedRW = [WriteFCom], Uses = [FPCW], mayRaiseFPException = 1 in {
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def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">;
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def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">;
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} // SchedRW
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let SchedRW = [WriteFMul], Defs = [FPSW], Uses = [FPCW] in {
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let SchedRW = [WriteFMul], Uses = [FPCW], mayRaiseFPException = 1 in {
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def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">;
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def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">;
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def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">;
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} // SchedRW
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let SchedRW = [WriteFDiv], Defs = [FPSW], Uses = [FPCW] in {
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let SchedRW = [WriteFDiv], Uses = [FPCW], mayRaiseFPException = 1 in {
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def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">;
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def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">;
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def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">;
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@ -359,13 +359,12 @@ def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
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def _F : FPI<0xD9, fp, (outs), (ins), asmstring>;
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}
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let Defs = [FPSW], Uses = [FPCW] in {
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let SchedRW = [WriteFSign] in {
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defm CHS : FPUnary<fneg, MRM_E0, "fchs">;
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defm ABS : FPUnary<fabs, MRM_E1, "fabs">;
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}
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let Uses = [FPCW], mayRaiseFPException = 1 in {
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let SchedRW = [WriteFSqrt80] in
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defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt">;
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@ -378,11 +377,11 @@ def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
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def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">;
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} // SchedRW
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} // Defs = [FPSW]
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} // Uses = [FPCW], mayRaiseFPException = 1
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// Versions of FP instructions that take a single memory operand. Added for the
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// disassembler; remove as they are included with patterns elsewhere.
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let SchedRW = [WriteFComLd], Defs = [FPSW], Uses = [FPCW] in {
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let SchedRW = [WriteFComLd], Uses = [FPCW], mayRaiseFPException = 1 in {
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def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">;
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def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">;
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@ -397,14 +396,21 @@ def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">;
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} // SchedRW
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let SchedRW = [WriteMicrocoded] in {
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let Defs = [FPSW, FPCW] in {
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def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;
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def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">;
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def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">;
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}
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let Defs = [FPSW, FPCW], Uses = [FPSW, FPCW] in {
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def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">;
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def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">;
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}
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let Uses = [FPSW] in
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def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">;
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def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">;
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let Uses = [FPCW] ,mayRaiseFPException = 1 in
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def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">;
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} // SchedRW
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@ -430,7 +436,6 @@ multiclass FPCMov<PatLeaf cc> {
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Requires<[HasCMov]>;
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}
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let Defs = [FPSW] in {
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let SchedRW = [WriteFCMOV] in {
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let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
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defm CMOVB : FPCMov<X86_COND_B>;
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@ -464,6 +469,7 @@ def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op),
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} // Predicates = [HasCMov]
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} // SchedRW
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let mayRaiseFPException = 1 in {
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// Floating point loads & stores.
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let SchedRW = [WriteLoad], Uses = [FPCW] in {
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let canFoldAsLoad = 1 in {
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@ -480,6 +486,7 @@ def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
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[(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;
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def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,
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[(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;
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let mayRaiseFPException = 0 in {
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def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
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[(set RFP32:$dst, (X86fild16 addr:$src))]>;
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def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
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@ -498,6 +505,7 @@ def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
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[(set RFP80:$dst, (X86fild32 addr:$src))]>;
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def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
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[(set RFP80:$dst, (X86fild64 addr:$src))]>;
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} // mayRaiseFPException = 0
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} // SchedRW
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let SchedRW = [WriteStore], Uses = [FPCW] in {
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@ -541,10 +549,12 @@ let mayLoad = 1, SchedRW = [WriteLoad], Uses = [FPCW] in {
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def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
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def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
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def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
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let mayRaiseFPException = 0 in {
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def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
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def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
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def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
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}
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}
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let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in {
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def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
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def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
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@ -616,7 +626,7 @@ def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">;
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let SchedRW = [WriteFLD1], Uses = [FPCW] in
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def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">;
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let SchedRW = [WriteFLDC], Uses = [FPCW] in {
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let SchedRW = [WriteFLDC], Defs = [FPSW], Uses = [FPCW] in {
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def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>;
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def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>;
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def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>;
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@ -633,11 +643,11 @@ def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
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def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
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[(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>;
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} // SchedRW
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} // Defs = [FPSW]
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} // mayRaiseFPException = 1
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let SchedRW = [WriteFCom] in {
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let SchedRW = [WriteFCom], mayRaiseFPException = 1 in {
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// CC = ST(0) cmp ST(i)
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let Defs = [EFLAGS, FPSW], Uses = [FPCW] in {
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let Defs = [EFLAGS, FPCW], Uses = [FPCW] in {
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def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
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[(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>,
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Requires<[FPStackf32, HasCMov]>;
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@ -649,7 +659,7 @@ def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
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Requires<[HasCMov]>;
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}
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let Defs = [FPSW], Uses = [ST0, FPCW] in {
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let Uses = [ST0, FPCW] in {
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def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i)
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(outs), (ins RSTi:$reg), "fucom\t$reg">;
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def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop
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@ -673,7 +683,7 @@ def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg),
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// Floating point flag ops.
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let SchedRW = [WriteALU] in {
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let Defs = [AX], Uses = [FPSW] in
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let Defs = [AX, FPSW], Uses = [FPSW] in
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def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags
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(outs), (ins), "fnstsw\t{%ax|ax}",
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[(set AX, (X86fp_stsw FPSW))]>;
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@ -689,31 +699,33 @@ def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
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// FPU control instructions
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let SchedRW = [WriteMicrocoded] in {
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let Defs = [FPSW] in {
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def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>;
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def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">;
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def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">;
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let Defs = [FPSW, FPCW] in
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def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>;
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// Clear exceptions
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let Defs = [FPSW] in
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def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>;
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} // Defs = [FPSW]
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} // SchedRW
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// Operand-less floating-point instructions for the disassembler.
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let Defs = [FPSW] in
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def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>;
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let SchedRW = [WriteMicrocoded] in {
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let Defs = [FPSW] in {
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def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
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def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", []>;
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def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>;
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def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>;
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let Uses = [FPCW], mayRaiseFPException = 1 in {
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def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>;
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def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>;
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def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>;
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def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>;
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def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>;
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def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>;
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def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>;
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def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>;
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def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>;
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def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>;
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def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>;
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@ -722,20 +734,26 @@ def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>;
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def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>;
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def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>;
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def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>;
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} // Uses = [FPCW], mayRaiseFPException = 1
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} // Defs = [FPSW]
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let Uses = [FPSW, FPCW] in {
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def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst),
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"fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, TB,
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Requires<[HasFXSR]>;
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def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst),
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"fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>,
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TB, Requires<[HasFXSR, In64BitMode]>;
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} // Uses = [FPSW, FPCW]
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let Defs = [FPSW, FPCW] in {
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def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src),
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"fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>,
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TB, Requires<[HasFXSR]>;
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def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src),
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"fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>,
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TB, Requires<[HasFXSR, In64BitMode]>;
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} // Defs = [FPSW, FPCW]
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} // SchedRW
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//===----------------------------------------------------------------------===//
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@ -442,12 +442,15 @@ class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
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// FPStack Instruction Templates:
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// FPI - Floating Point Instruction template.
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class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
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: I<o, F, outs, ins, asm, []> {}
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: I<o, F, outs, ins, asm, []> {
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let Defs = [FPSW];
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}
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// FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
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class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
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: PseudoI<outs, ins, pattern> {
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let FPForm = fp;
|
||||
let Defs = [FPSW];
|
||||
}
|
||||
|
||||
// Templates for instructions that use a 16- or 32-bit segmented address as
|
||||
|
|
|
|||
|
|
@ -0,0 +1,248 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -march=x86-64 -mattr=+x87 -mattr=-sse -run-pass none -o - %s | FileCheck %s
|
||||
# This test ensures that the MIR parser parses the x87 fpsw and fpcw regs
|
||||
|
||||
--- |
|
||||
declare float @llvm.sqrt.f32(float)
|
||||
|
||||
define void @f1(float* %a, float* %b) {
|
||||
%1 = load float, float* %a, align 4
|
||||
%2 = load float, float* %b, align 4
|
||||
%sub = fsub float %1, %2
|
||||
store float %sub, float* %a, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @f2(double* %a, double* %b) {
|
||||
%1 = load double, double* %a, align 8
|
||||
%2 = load double, double* %b, align 8
|
||||
%add = fadd double %1, %2
|
||||
store double %add, double* %a, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @f3(x86_fp80* %a, x86_fp80* %b) {
|
||||
%1 = load x86_fp80, x86_fp80* %a, align 16
|
||||
%2 = load x86_fp80, x86_fp80* %b, align 16
|
||||
%mul = fmul x86_fp80 %1, %2
|
||||
store x86_fp80 %mul, x86_fp80* %a, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @f4(float* %a, float* %b) {
|
||||
%1 = load float, float* %a, align 4
|
||||
%2 = load float, float* %b, align 4
|
||||
%div = fdiv float %1, %2
|
||||
store float %div, float* %a, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @f5(float* %val, double* %ret) {
|
||||
%1 = load float, float* %val, align 4
|
||||
%res = fpext float %1 to double
|
||||
store double %res, double* %ret, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @f6(double* %val, float* %ret) {
|
||||
%1 = load double, double* %val, align 8
|
||||
%res = fptrunc double %1 to float
|
||||
store float %res, float* %ret, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @f7(float* %a) {
|
||||
%1 = load float, float* %a, align 4
|
||||
%res = call float @llvm.sqrt.f32(float %1)
|
||||
store float %res, float* %a, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
||||
...
|
||||
---
|
||||
name: f1
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$rdi' }
|
||||
- { reg: '$rsi' }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: $rdi, $rsi
|
||||
|
||||
; CHECK-LABEL: name: f1
|
||||
; CHECK: liveins: $rdi, $rsi
|
||||
; CHECK: renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
|
||||
; CHECK: renamable $fp0 = SUB_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)
|
||||
; CHECK: ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
|
||||
; CHECK: RET 0
|
||||
renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
|
||||
renamable $fp0 = SUB_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)
|
||||
ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
|
||||
RET 0
|
||||
|
||||
...
|
||||
---
|
||||
name: f2
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$rdi' }
|
||||
- { reg: '$rsi' }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: $rdi, $rsi
|
||||
|
||||
; CHECK-LABEL: name: f2
|
||||
; CHECK: liveins: $rdi, $rsi
|
||||
; CHECK: renamable $fp0 = LD_Fp64m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.a)
|
||||
; CHECK: renamable $fp0 = ADD_Fp64m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.b)
|
||||
; CHECK: ST_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.a)
|
||||
; CHECK: RET 0
|
||||
renamable $fp0 = LD_Fp64m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.a)
|
||||
renamable $fp0 = ADD_Fp64m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.b)
|
||||
ST_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.a)
|
||||
RET 0
|
||||
|
||||
...
|
||||
---
|
||||
name: f3
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$rdi' }
|
||||
- { reg: '$rsi' }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: $rdi, $rsi
|
||||
|
||||
; CHECK-LABEL: name: f3
|
||||
; CHECK: liveins: $rdi, $rsi
|
||||
; CHECK: renamable $fp0 = LD_Fp80m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.a, align 16)
|
||||
; CHECK: renamable $fp1 = LD_Fp80m killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.b, align 16)
|
||||
; CHECK: renamable $fp0 = MUL_Fp80 killed renamable $fp0, killed renamable $fp1, implicit-def dead $fpsw, implicit $fpcw
|
||||
; CHECK: ST_FpP80m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 10 into %ir.a, align 16)
|
||||
; CHECK: RET 0
|
||||
renamable $fp0 = LD_Fp80m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.a, align 16)
|
||||
renamable $fp1 = LD_Fp80m killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.b, align 16)
|
||||
renamable $fp0 = MUL_Fp80 killed renamable $fp0, killed renamable $fp1, implicit-def dead $fpsw, implicit $fpcw
|
||||
ST_FpP80m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 10 into %ir.a, align 16)
|
||||
RET 0
|
||||
|
||||
...
|
||||
---
|
||||
name: f4
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$rdi' }
|
||||
- { reg: '$rsi' }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: $rdi, $rsi
|
||||
|
||||
; CHECK-LABEL: name: f4
|
||||
; CHECK: liveins: $rdi, $rsi
|
||||
; CHECK: renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
|
||||
; CHECK: renamable $fp0 = DIV_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)
|
||||
; CHECK: ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
|
||||
; CHECK: RET 0
|
||||
renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
|
||||
renamable $fp0 = DIV_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)
|
||||
ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
|
||||
RET 0
|
||||
|
||||
...
|
||||
---
|
||||
name: f5
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$rdi' }
|
||||
- { reg: '$rsi' }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: $rdi, $rsi
|
||||
|
||||
; CHECK-LABEL: name: f5
|
||||
; CHECK: liveins: $rdi, $rsi
|
||||
; CHECK: renamable $fp0 = LD_Fp32m64 killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.val)
|
||||
; CHECK: ST_Fp64m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.ret)
|
||||
; CHECK: RET 0
|
||||
renamable $fp0 = LD_Fp32m64 killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.val)
|
||||
ST_Fp64m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.ret)
|
||||
RET 0
|
||||
|
||||
...
|
||||
---
|
||||
name: f6
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$rdi' }
|
||||
- { reg: '$rsi' }
|
||||
frameInfo:
|
||||
maxAlignment: 4
|
||||
stack:
|
||||
- { id: 0, size: 4, alignment: 4 }
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: $rdi, $rsi
|
||||
|
||||
; CHECK-LABEL: name: f6
|
||||
; CHECK: liveins: $rdi, $rsi
|
||||
; CHECK: renamable $fp0 = LD_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.val)
|
||||
; CHECK: ST_Fp64m32 %stack.0, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %stack.0)
|
||||
; CHECK: renamable $fp0 = LD_Fp32m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %stack.0)
|
||||
; CHECK: ST_Fp32m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.ret)
|
||||
; CHECK: RET 0
|
||||
renamable $fp0 = LD_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.val)
|
||||
ST_Fp64m32 %stack.0, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %stack.0)
|
||||
renamable $fp0 = LD_Fp32m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %stack.0)
|
||||
ST_Fp32m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.ret)
|
||||
RET 0
|
||||
|
||||
...
|
||||
---
|
||||
name: f7
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$rdi' }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: $rdi
|
||||
|
||||
; CHECK-LABEL: name: f7
|
||||
; CHECK: liveins: $rdi
|
||||
; CHECK: renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
|
||||
; CHECK: renamable $fp0 = SQRT_Fp32 killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw
|
||||
; CHECK: ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
|
||||
; CHECK: RET 0
|
||||
renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
|
||||
renamable $fp0 = SQRT_Fp32 killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw
|
||||
ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
|
||||
RET 0
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue