From af397cec0b347074da72f3f31bdba74fac6a46c5 Mon Sep 17 00:00:00 2001
From: Nate Begeman <natebegeman@mac.com>
Date: Sat, 28 Jan 2006 01:06:30 +0000
Subject: [PATCH] Add a missing case to the dag combiner.

llvm-svn: 25723
---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 99c272e00137..a96c59b3400b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1035,9 +1035,10 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
     WorkList.push_back(ANDNode.Val);
     return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
   }
-  // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y))
+  // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y))
   if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
-       (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) &&
+       (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
+       (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
       N0.getOperand(1) == N1.getOperand(1)) {
     SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
                                     N0.getOperand(0), N1.getOperand(0));