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Significant changes to correctly spill CC registers and to correctly 

handle conditional move instructions:
-- cpMem<->Reg functions now support CC registers (int and FP) correctly.
   Also, cpMem<->Reg functions now return a vector of machine instructions.
-- Scratch registers must be explicitly provided to cpMem<->Reg when
   needed, since CC regs need one to be copied to/from memory.
-- CC regs are saved to a scratch register instead of stack.
-- All regs used by a instruction are now recorded in MachineInstr::regsUsed,
   since regs used to save values *across* an instruction are not obvious
   either from the operands or from the LiveVar sets.
-- An (explicit or implicit) operand may now be both a def and a use.
   This is needed for conditional move operations.
   So an operand may need spill code both before and after the instruction.

Other changes:
-- Added several get{Class,Type} functions.
-- Added unified-to-local register number conversion.
-- class MachineCodeForBasicBlock is now an annotation on BasicBlock.
-- Suggest/Color methods may modify the MachineInstr (and always did),
   so don't make that argument const!
-- Caller-saving code doesn't need its special purpose code for
   handling CC registers since cpMem<->Reg handle those correctly now.

llvm-svn: 2834
This commit is contained in:
Vikram S. Adve 2002-07-08 23:23:12 +00:00
parent 7228f0c404
commit aee6701e63
1 changed files with 273 additions and 214 deletions
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487
llvm/lib/Target/Sparc/SparcRegInfo.cpp
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@ -11,6 +11,7 @@
#include "llvm/CodeGen/MachineCodeForMethod.h" #include "llvm/CodeGen/MachineCodeForMethod.h"
#include "llvm/CodeGen/PhyRegAlloc.h" #include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/InstrSelection.h"
#include "llvm/CodeGen/InstrSelectionSupport.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrAnnot.h" #include "llvm/CodeGen/MachineInstrAnnot.h"
#include "llvm/CodeGen/RegAllocCommon.h" #include "llvm/CodeGen/RegAllocCommon.h"
@ -32,7 +33,7 @@ UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID)); MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID)); MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID)); MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
assert(SparcFloatRegOrder::StartOfNonVolatileRegs == 32 && assert(SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
"32 Float regs are used for float arg passing"); "32 Float regs are used for float arg passing");
} }
@ -175,7 +176,7 @@ UltraSparcRegInfo::regNumForFPArg(unsigned regType,
// Finds the return address of a call sparc specific call instruction // Finds the return address of a call sparc specific call instruction
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
// The following 4 methods are used to find the RegType (see enum above) // The following 4 methods are used to find the RegType (SparcInternals.h)
// of a LiveRange, a Value, and for a given register unified reg number. // of a LiveRange, a Value, and for a given register unified reg number.
// //
int UltraSparcRegInfo::getRegType(unsigned regClassID, int UltraSparcRegInfo::getRegType(unsigned regClassID,
@ -203,38 +204,81 @@ int UltraSparcRegInfo::getRegType(const Value *Val) const {
return getRegType(getRegClassIDOfValue(Val), Val->getType()); return getRegType(getRegClassIDOfValue(Val), Val->getType());
} }
int UltraSparcRegInfo::getRegType(int reg) const { int UltraSparcRegInfo::getRegType(int unifiedRegNum) const {
if (reg < 32) if (unifiedRegNum < 32)
return IntRegType; return IntRegType;
else if (reg < (32 + 32)) else if (unifiedRegNum < (32 + 32))
return FPSingleRegType; return FPSingleRegType;
else if (reg < (64 + 32)) else if (unifiedRegNum < (64 + 32))
return FPDoubleRegType; return FPDoubleRegType;
else if (reg < (64+32+4)) else if (unifiedRegNum < (64+32+4))
return FloatCCRegType; return FloatCCRegType;
else if (reg < (64+32+4+2)) else if (unifiedRegNum < (64+32+4+2))
return IntCCRegType; return IntCCRegType;
else else
assert(0 && "Invalid register number in getRegType"); assert(0 && "Invalid unified register number in getRegType");
return 0; return 0;
} }
// To find the register class used for a specified Type
//
unsigned UltraSparcRegInfo::getRegClassIDOfType(const Type *type,
bool isCCReg = false) const {
Type::PrimitiveID ty = type->getPrimitiveID();
unsigned res;
// FIXME: Comparing types like this isn't very safe...
if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
(ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
res = IntRegClassID; // sparc int reg (ty=0: void)
else if (ty <= Type::DoubleTyID)
res = FloatRegClassID; // sparc float reg class
else {
//std::cerr << "TypeID: " << ty << "\n";
assert(0 && "Cannot resolve register class for type");
return 0;
}
if(isCCReg)
return res + 2; // corresponidng condition code regiser
else
return res;
}
// To find the register class to which a specified register belongs
//
unsigned UltraSparcRegInfo::getRegClassIDOfReg(int unifiedRegNum) const {
unsigned classId = 0;
(void) getClassRegNum(unifiedRegNum, classId);
return classId;
}
unsigned UltraSparcRegInfo::getRegClassIDOfRegType(int regType) const {
switch(regType) {
case IntRegType: return IntRegClassID;
case FPSingleRegType:
case FPDoubleRegType: return FloatRegClassID;
case IntCCRegType: return IntCCRegClassID;
case FloatCCRegType: return FloatCCRegClassID;
default:
assert(0 && "Invalid register type in getRegClassIDOfRegType");
return 0;
}
}
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
// Suggests a register for the ret address in the RET machine instruction. // Suggests a register for the ret address in the RET machine instruction.
// We always suggest %i7 by convention. // We always suggest %i7 by convention.
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr *RetMI, void UltraSparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
LiveRangeInfo& LRI) const { LiveRangeInfo& LRI) const {
assert( (RetMI->getNumOperands() >= 2) assert(target.getInstrInfo().isReturn(RetMI->getOpCode()));
&& "JMPL/RETURN must have 3 and 2 operands respectively");
MachineOperand & MO = ( MachineOperand &) RetMI->getOperand(0); // return address is always mapped to i7 so set it immediately
RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
// return address is always mapped to i7 SparcIntRegOrder::i7));
//
MO.setRegForValue( getUnifiedRegNum( IntRegClassID, SparcIntRegOrder::i7) );
// Possible Optimization: // Possible Optimization:
// Instead of setting the color, we can suggest one. In that case, // Instead of setting the color, we can suggest one. In that case,
@ -242,11 +286,12 @@ void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr *RetMI,
// In that case, a LR has to be created at the start of method. // In that case, a LR has to be created at the start of method.
// It has to be done as follows (remove the setRegVal above): // It has to be done as follows (remove the setRegVal above):
// MachineOperand & MO = RetMI->getOperand(0);
// const Value *RetAddrVal = MO.getVRegValue(); // const Value *RetAddrVal = MO.getVRegValue();
// assert( RetAddrVal && "LR for ret address must be created at start"); // assert( RetAddrVal && "LR for ret address must be created at start");
// LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal); // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
// RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID, // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
// SparcIntRegOrdr::i7) ); // SparcIntRegOrdr::i7) );
} }
@ -254,7 +299,7 @@ void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr *RetMI,
// Suggests a register for the ret address in the JMPL/CALL machine instr. // Suggests a register for the ret address in the JMPL/CALL machine instr.
// Sparc ABI dictates that %o7 be used for this purpose. // Sparc ABI dictates that %o7 be used for this purpose.
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
void UltraSparcRegInfo::suggestReg4CallAddr(const MachineInstr * CallMI, void UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
LiveRangeInfo& LRI, LiveRangeInfo& LRI,
std::vector<RegClass *> RCList) const { std::vector<RegClass *> RCList) const {
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
@ -384,14 +429,14 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
int TmpOff = MachineCodeForMethod::get(Meth).pushTempValue(target, int TmpOff = MachineCodeForMethod::get(Meth).pushTempValue(target,
getSpilledRegSize(regType)); getSpilledRegSize(regType));
cpReg2MemMI(UniArgReg, getFramePointer(), TmpOff, IntRegType, cpReg2MemMI(FirstAI->InstrnsBefore,
FirstAI->InstrnsBefore); UniArgReg, getFramePointer(), TmpOff, IntRegType);
cpMem2RegMI(getFramePointer(), TmpOff, UniLRReg, regType, cpMem2RegMI(FirstAI->InstrnsBefore,
FirstAI->InstrnsBefore); getFramePointer(), TmpOff, UniLRReg, regType);
} }
else { else {
cpReg2RegMI(UniArgReg, UniLRReg, regType, FirstAI->InstrnsBefore); cpReg2RegMI(FirstAI->InstrnsBefore, UniArgReg, UniLRReg, regType);
} }
} }
else { else {
@ -404,8 +449,8 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth), frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
argNo); argNo);
cpMem2RegMI(getFramePointer(), offsetFromFP, UniLRReg, regType, cpMem2RegMI(FirstAI->InstrnsBefore,
FirstAI->InstrnsBefore); getFramePointer(), offsetFromFP, UniLRReg, regType);
} }
} // if LR received a color } // if LR received a color
@ -430,12 +475,12 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
assert(isVarArgs && regClassIDOfArgReg == IntRegClassID && assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
"This should only be an Int register for an FP argument"); "This should only be an Int register for an FP argument");
cpReg2MemMI(UniArgReg, getFramePointer(), LR->getSpillOffFromFP(), cpReg2MemMI(FirstAI->InstrnsBefore, UniArgReg,
IntRegType, FirstAI->InstrnsBefore); getFramePointer(), LR->getSpillOffFromFP(), IntRegType);
} }
else { else {
cpReg2MemMI(UniArgReg, getFramePointer(), LR->getSpillOffFromFP(), cpReg2MemMI(FirstAI->InstrnsBefore, UniArgReg,
regType, FirstAI->InstrnsBefore); getFramePointer(), LR->getSpillOffFromFP(), regType);
} }
} }
@ -467,7 +512,7 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
// This method is called before graph coloring to suggest colors to the // This method is called before graph coloring to suggest colors to the
// outgoing call args and the return value of the call. // outgoing call args and the return value of the call.
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *CallMI, void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
LiveRangeInfo& LRI, LiveRangeInfo& LRI,
std::vector<RegClass *> RCList) const { std::vector<RegClass *> RCList) const {
assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) ); assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
@ -574,7 +619,7 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *CallMI,
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
void void
UltraSparcRegInfo::InitializeOutgoingArg(const MachineInstr* CallMI, UltraSparcRegInfo::InitializeOutgoingArg(MachineInstr* CallMI,
AddedInstrns *CallAI, AddedInstrns *CallAI,
PhyRegAlloc &PRA, LiveRange* LR, PhyRegAlloc &PRA, LiveRange* LR,
unsigned regType, unsigned RegClassID, unsigned regType, unsigned RegClassID,
@ -589,6 +634,7 @@ UltraSparcRegInfo::InitializeOutgoingArg(const MachineInstr* CallMI,
{ {
isArgInReg = true; isArgInReg = true;
UniArgReg = (unsigned) UniArgRegOrNone; UniArgReg = (unsigned) UniArgRegOrNone;
CallMI->getRegsUsed().insert(UniArgReg); // mark the reg as used
} }
if (LR->hasColor()) { if (LR->hasColor()) {
@ -603,22 +649,22 @@ UltraSparcRegInfo::InitializeOutgoingArg(const MachineInstr* CallMI,
// //
if( isArgInReg ) { if( isArgInReg ) {
// Copy UniLRReg to UniArgReg // Copy UniLRReg to UniArgReg
cpReg2RegMI(UniLRReg, UniArgReg, regType, AddedInstrnsBefore); cpReg2RegMI(AddedInstrnsBefore, UniLRReg, UniArgReg, regType);
} }
else { else {
// Copy UniLRReg to the stack to pass the arg on stack. // Copy UniLRReg to the stack to pass the arg on stack.
const MachineFrameInfo& frameInfo = target.getFrameInfo(); const MachineFrameInfo& frameInfo = target.getFrameInfo();
int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo); int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
cpReg2MemMI(UniLRReg, getStackPointer(), argOffset, regType, cpReg2MemMI(CallAI->InstrnsBefore,
CallAI->InstrnsBefore); UniLRReg, getStackPointer(), argOffset, regType);
} }
} else { // LR is not colored (i.e., spilled) } else { // LR is not colored (i.e., spilled)
if( isArgInReg ) { if( isArgInReg ) {
// Insert a load instruction to load the LR to UniArgReg // Insert a load instruction to load the LR to UniArgReg
cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(), cpMem2RegMI(AddedInstrnsBefore, getFramePointer(),
UniArgReg, regType, AddedInstrnsBefore); LR->getSpillOffFromFP(), UniArgReg, regType);
// Now add the instruction // Now add the instruction
} }
@ -651,14 +697,14 @@ UltraSparcRegInfo::InitializeOutgoingArg(const MachineInstr* CallMI,
// //
// NOTE: We directly add to CallAI->InstrnsBefore instead of adding to // NOTE: We directly add to CallAI->InstrnsBefore instead of adding to
// AddedInstrnsBefore since these instructions must not be reordered. // AddedInstrnsBefore since these instructions must not be reordered.
cpReg2MemMI(TReg, getFramePointer(), TmpOff, regType, cpReg2MemMI(CallAI->InstrnsBefore,
CallAI->InstrnsBefore); TReg, getFramePointer(), TmpOff, regType);
cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(), TReg, regType, cpMem2RegMI(CallAI->InstrnsBefore,
CallAI->InstrnsBefore); getFramePointer(), LR->getSpillOffFromFP(), TReg, regType);
cpReg2MemMI(TReg, getStackPointer(), argOffset, regType, cpReg2MemMI(CallAI->InstrnsBefore,
CallAI->InstrnsBefore); TReg, getStackPointer(), argOffset, regType);
cpMem2RegMI(getFramePointer(), TmpOff, TReg, regType, cpMem2RegMI(CallAI->InstrnsBefore,
CallAI->InstrnsBefore); getFramePointer(), TmpOff, TReg, regType);
} }
} }
} }
@ -669,7 +715,7 @@ UltraSparcRegInfo::InitializeOutgoingArg(const MachineInstr* CallMI,
// to instert copy instructions. // to instert copy instructions.
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
void UltraSparcRegInfo::colorCallArgs(const MachineInstr *CallMI, void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI,
LiveRangeInfo &LRI, LiveRangeInfo &LRI,
AddedInstrns *CallAI, AddedInstrns *CallAI,
PhyRegAlloc &PRA, PhyRegAlloc &PRA,
@ -708,16 +754,16 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *CallMI,
return; return;
} }
// Mark the register as used by this instruction
CallMI->getRegsUsed().insert(this->getUnifiedRegNum(RegClassID,CorrectCol));
// if the LR received the correct color, NOTHING to do // if the LR received the correct color, NOTHING to do
if( RetValLR->hasColor() ) if( RetValLR->hasColor() )
if( RetValLR->getColor() == CorrectCol ) if( RetValLR->getColor() == CorrectCol )
recvCorrectColor = true; recvCorrectColor = true;
// if we didn't receive the correct color for some reason, // if we didn't receive the correct color for some reason,
// put copy instruction // put copy instruction
if( !recvCorrectColor ) { if( !recvCorrectColor ) {
unsigned regType = getRegType( RetValLR ); unsigned regType = getRegType( RetValLR );
@ -733,7 +779,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *CallMI,
// the return value is coming in UniRetReg but has to go into // the return value is coming in UniRetReg but has to go into
// the UniRetLRReg // the UniRetLRReg
cpReg2RegMI(UniRetReg, UniRetLRReg, regType, CallAI->InstrnsAfter); cpReg2RegMI(CallAI->InstrnsAfter, UniRetReg, UniRetLRReg, regType);
} // if LR has color } // if LR has color
else { else {
@ -741,8 +787,8 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *CallMI,
// if the LR did NOT receive a color, we have to move the return // if the LR did NOT receive a color, we have to move the return
// value coming in UniRetReg to the stack pos of spilled LR // value coming in UniRetReg to the stack pos of spilled LR
cpReg2MemMI(UniRetReg, getFramePointer(),RetValLR->getSpillOffFromFP(), cpReg2MemMI(CallAI->InstrnsAfter, UniRetReg,
regType, CallAI->InstrnsAfter); getFramePointer(),RetValLR->getSpillOffFromFP(), regType);
} }
} // the LR didn't receive the suggested color } // the LR didn't receive the suggested color
@ -862,12 +908,12 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *CallMI,
// This method is called for an LLVM return instruction to identify which // This method is called for an LLVM return instruction to identify which
// values will be returned from this method and to suggest colors. // values will be returned from this method and to suggest colors.
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *RetMI, void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
LiveRangeInfo &LRI) const { LiveRangeInfo &LRI) const {
assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) ); assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
suggestReg4RetAddr(RetMI, LRI); suggestReg4RetAddr(RetMI, LRI);
// if there is an implicit ref, that has to be the ret value // if there is an implicit ref, that has to be the ret value
if( RetMI->getNumImplicitRefs() > 0 ) { if( RetMI->getNumImplicitRefs() > 0 ) {
@ -899,7 +945,7 @@ void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *RetMI,
// the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we // the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
// have to put a load instruction. // have to put a load instruction.
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
void UltraSparcRegInfo::colorRetValue(const MachineInstr *RetMI, void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI,
LiveRangeInfo &LRI, LiveRangeInfo &LRI,
AddedInstrns *RetAI) const { AddedInstrns *RetAI) const {
@ -932,6 +978,9 @@ void UltraSparcRegInfo::colorRetValue(const MachineInstr *RetMI,
return; return;
} }
// Mark the register as used by this instruction
RetMI->getRegsUsed().insert(this->getUnifiedRegNum(RegClassID, CorrectCol));
// if the LR received the correct color, NOTHING to do // if the LR received the correct color, NOTHING to do
if (LR->hasColor() && LR->getColor() == CorrectCol) if (LR->hasColor() && LR->getColor() == CorrectCol)
@ -950,11 +999,11 @@ void UltraSparcRegInfo::colorRetValue(const MachineInstr *RetMI,
// the LR received UniLRReg but must be colored with UniRetReg // the LR received UniLRReg but must be colored with UniRetReg
// to pass as the return value // to pass as the return value
cpReg2RegMI(UniLRReg, UniRetReg, regType, RetAI->InstrnsBefore); cpReg2RegMI(RetAI->InstrnsBefore, UniLRReg, UniRetReg, regType);
} }
else { // if the LR is spilled else { // if the LR is spilled
cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(), cpMem2RegMI(RetAI->InstrnsBefore, getFramePointer(),
UniRetReg, regType, RetAI->InstrnsBefore); LR->getSpillOffFromFP(), UniRetReg, regType);
cerr << "\nCopied the return value from stack\n"; cerr << "\nCopied the return value from stack\n";
} }
@ -962,17 +1011,37 @@ void UltraSparcRegInfo::colorRetValue(const MachineInstr *RetMI,
} }
//---------------------------------------------------------------------------
// Check if a specified register type needs a scratch register to be
// copied to/from memory. If it does, the reg. type that must be used
// for scratch registers is returned in scratchRegType.
//
// Only the int CC register needs such a scratch register.
// The FP CC registers can (and must) be copied directly to/from memory.
//---------------------------------------------------------------------------
bool
UltraSparcRegInfo::regTypeNeedsScratchReg(int RegType,
int& scratchRegType) const
{
if (RegType == IntCCRegType)
{
scratchRegType = IntRegType;
return true;
}
return false;
}
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
// Copy from a register to register. Register number must be the unified // Copy from a register to register. Register number must be the unified
// register number // register number.
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
void void
UltraSparcRegInfo::cpReg2RegMI(unsigned SrcReg, UltraSparcRegInfo::cpReg2RegMI(vector<MachineInstr*>& mvec,
unsigned SrcReg,
unsigned DestReg, unsigned DestReg,
int RegType, int RegType) const {
vector<MachineInstr*>& mvec) const {
assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) && assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
"Invalid Register"); "Invalid Register");
@ -981,31 +1050,39 @@ UltraSparcRegInfo::cpReg2RegMI(unsigned SrcReg,
switch( RegType ) { switch( RegType ) {
case IntCCRegType: case IntCCRegType:
if (this->getRegType(DestReg) == IntRegType)
{ // copy intCC reg to int reg
// Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, DestReg);
}
else
{ // copy int reg to intCC reg
// Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
assert(this->getRegType(SrcReg) == IntRegType
&& "Can only copy CC reg to/from integer reg");
MI = Create2OperandInstr_Reg(WRCCR, SrcReg, DestReg+1);
}
break;
case FloatCCRegType: case FloatCCRegType:
assert(0 && "This code was bogus and needs to be fixed!"); assert(0 && "Cannot copy FPCC register to any other register");
break; break;
case IntRegType: case IntRegType:
MI = new MachineInstr(ADD, 3); MI = Create3OperandInstr_Reg(ADD, SrcReg, this->getZeroRegNum(), DestReg);
MI->SetMachineOperandReg(0, SrcReg, false);
MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
MI->SetMachineOperandReg(2, DestReg, true);
break; break;
case FPSingleRegType: case FPSingleRegType:
MI = new MachineInstr(FMOVS, 2); MI = Create2OperandInstr_Reg(FMOVS, SrcReg, DestReg);
MI->SetMachineOperandReg(0, SrcReg, false);
MI->SetMachineOperandReg(1, DestReg, true);
break; break;
case FPDoubleRegType: case FPDoubleRegType:
MI = new MachineInstr(FMOVD, 2); MI = Create2OperandInstr_Reg(FMOVD, SrcReg, DestReg);
MI->SetMachineOperandReg(0, SrcReg, false);
MI->SetMachineOperandReg(1, DestReg, true);
break; break;
default: default:
assert(0 && "Unknown RegType"); assert(0 && "Unknown RegType");
break;
} }
if (MI) if (MI)
@ -1019,19 +1096,20 @@ UltraSparcRegInfo::cpReg2RegMI(unsigned SrcReg,
void void
UltraSparcRegInfo::cpReg2MemMI(unsigned SrcReg, UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
unsigned SrcReg,
unsigned DestPtrReg, unsigned DestPtrReg,
int Offset, int RegType, int Offset, int RegType,
vector<MachineInstr*>& mvec) const { int scratchReg = -1) const {
MachineInstr * MI = NULL; MachineInstr * MI = NULL;
switch( RegType ) { switch( RegType ) {
case IntRegType: case IntRegType:
case FloatCCRegType:
MI = new MachineInstr(STX, 3); MI = new MachineInstr(STX, 3);
MI->SetMachineOperandReg(0, SrcReg, false); MI->SetMachineOperandReg(0, SrcReg, false);
MI->SetMachineOperandReg(1, DestPtrReg, false); MI->SetMachineOperandReg(1, DestPtrReg, false);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed, MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset); (int64_t) Offset);
mvec.push_back(MI);
break; break;
case FPSingleRegType: case FPSingleRegType:
@ -1040,6 +1118,7 @@ UltraSparcRegInfo::cpReg2MemMI(unsigned SrcReg,
MI->SetMachineOperandReg(1, DestPtrReg, false); MI->SetMachineOperandReg(1, DestPtrReg, false);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed, MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset); (int64_t) Offset);
mvec.push_back(MI);
break; break;
case FPDoubleRegType: case FPDoubleRegType:
@ -1048,17 +1127,33 @@ UltraSparcRegInfo::cpReg2MemMI(unsigned SrcReg,
MI->SetMachineOperandReg(1, DestPtrReg, false); MI->SetMachineOperandReg(1, DestPtrReg, false);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed, MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset); (int64_t) Offset);
mvec.push_back(MI);
break; break;
case IntCCRegType: case IntCCRegType:
assert( 0 && "Cannot directly store %ccr to memory"); assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory");
assert(this->getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
// Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, scratchReg);
mvec.push_back(MI);
this->cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType);
break;
case FloatCCRegType:
assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
MI = new MachineInstr(STXFSR, 3);
MI->SetMachineOperandReg(0, SrcReg, false);
MI->SetMachineOperandReg(1, DestPtrReg, false);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
mvec.push_back(MI);
break;
default: default:
assert(0 && "Unknown RegType in cpReg2MemMI"); assert(0 && "Unknown RegType in cpReg2MemMI");
} }
if (MI)
mvec.push_back(MI);
} }
@ -1069,20 +1164,21 @@ UltraSparcRegInfo::cpReg2MemMI(unsigned SrcReg,
void void
UltraSparcRegInfo::cpMem2RegMI(unsigned SrcPtrReg, UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
unsigned SrcPtrReg,
int Offset, int Offset,
unsigned DestReg, unsigned DestReg,
int RegType, int RegType,
vector<MachineInstr*>& mvec) const { int scratchReg = -1) const {
MachineInstr * MI = NULL; MachineInstr * MI = NULL;
switch (RegType) { switch (RegType) {
case IntRegType: case IntRegType:
case FloatCCRegType:
MI = new MachineInstr(LDX, 3); MI = new MachineInstr(LDX, 3);
MI->SetMachineOperandReg(0, SrcPtrReg, false); MI->SetMachineOperandReg(0, SrcPtrReg, false);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset); (int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true); MI->SetMachineOperandReg(2, DestReg, true);
mvec.push_back(MI);
break; break;
case FPSingleRegType: case FPSingleRegType:
@ -1091,7 +1187,7 @@ UltraSparcRegInfo::cpMem2RegMI(unsigned SrcPtrReg,
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset); (int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true); MI->SetMachineOperandReg(2, DestReg, true);
mvec.push_back(MI);
break; break;
case FPDoubleRegType: case FPDoubleRegType:
@ -1100,17 +1196,33 @@ UltraSparcRegInfo::cpMem2RegMI(unsigned SrcPtrReg,
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset); (int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true); MI->SetMachineOperandReg(2, DestReg, true);
mvec.push_back(MI);
break; break;
case IntCCRegType: case IntCCRegType:
assert( 0 && "Cannot directly load into %ccr from memory"); assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory");
assert(this->getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
this->cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType);
// Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
MI = Create2OperandInstr_Reg(WRCCR, scratchReg, DestReg+1);
mvec.push_back(MI);
break;
case FloatCCRegType:
assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
MI = new MachineInstr(LDXFSR, 3);
MI->SetMachineOperandReg(0, SrcPtrReg, false);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
mvec.push_back(MI);
break;
default: default:
assert(0 && "Unknown RegType in cpMem2RegMI"); assert(0 && "Unknown RegType in cpMem2RegMI");
} }
if (MI)
mvec.push_back(MI);
} }
@ -1178,7 +1290,7 @@ UltraSparcRegInfo::cpValue2Value(Value *Src,
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *CallMI, void UltraSparcRegInfo::insertCallerSavingCode(MachineInstr *CallMI,
const BasicBlock *BB, const BasicBlock *BB,
PhyRegAlloc &PRA) const { PhyRegAlloc &PRA) const {
@ -1233,7 +1345,7 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *CallMI,
// if the value is in both LV sets (i.e., live before and after // if the value is in both LV sets (i.e., live before and after
// the call machine instruction) // the call machine instruction)
unsigned Reg = getUnifiedRegNum(RCID, Color); unsigned Reg = getUnifiedRegNum(RCID, Color);
if( PushedRegSet.find(Reg) == PushedRegSet.end() ) { if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
@ -1245,107 +1357,84 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *CallMI,
// Now get two instructions - to push on stack and pop from stack // Now get two instructions - to push on stack and pop from stack
// and add them to InstrnsBefore and InstrnsAfter of the // and add them to InstrnsBefore and InstrnsAfter of the
// call instruction // call instruction
//
int StackOff = PRA.mcInfo.pushTempValue(target, int StackOff = PRA.mcInfo.pushTempValue(target,
getSpilledRegSize(RegType)); getSpilledRegSize(RegType));
MachineInstr *AdIBefCC=NULL, *AdIAftCC=NULL, *AdICpCC; vector<MachineInstr*>& instrnsBefore =
MachineInstr *AdIBef=NULL, *AdIAft=NULL; PRA.AddedInstrMap[CallMI].InstrnsBefore;
vector<MachineInstr*>& instrnsAfter =
PRA.AddedInstrMap[CallMI].InstrnsAfter;
vector<MachineInstr*> AdIBef, AdIAft;
//---- Insert code for pushing the reg on stack ---------- //---- Insert code for pushing the reg on stack ----------
if( RegType == IntCCRegType ) { // We may need a scratch register to copy the saved value
// to/from memory. This may itself have to insert code to
// Handle IntCCRegType specially since we cannot directly // free up a scratch register. Any such code should go before
// push %ccr on to the stack // the save code.
int scratchRegType = -1;
const ValueSet &LVSetBef = int scratchReg = -1;
PRA.LVI->getLiveVarSetBeforeMInst(CallMI, BB); if (this->regTypeNeedsScratchReg(RegType, scratchRegType))
{ // Find a register not live in the LVSet before CallMI
// get a free INTEGER register const ValueSet &LVSetBef =
int FreeIntReg = PRA.LVI->getLiveVarSetBeforeMInst(CallMI, BB);
PRA.getUsableUniRegAtMI(PRA.getRegClassByID(IntRegClassID) /*LR->getRegClass()*/, scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetBef,
IntRegType, CallMI, &LVSetBef, AdIBefCC, AdIAftCC); CallMI, AdIBef, AdIAft);
assert(scratchReg != this->getInvalidRegNum());
// insert the instructions in reverse order since we are CallMI->getRegsUsed().insert(scratchReg);
// adding them to the front of InstrnsBefore }
AddedInstrns& addedI = PRA.AddedInstrMap[CallMI];
if(AdIAftCC) if (AdIBef.size() > 0)
addedI.InstrnsBefore.insert(addedI.InstrnsBefore.begin(), instrnsBefore.insert(instrnsBefore.end(),
AdIAftCC); AdIBef.begin(), AdIBef.end());
AdICpCC = cpCCR2IntMI(FreeIntReg); cpReg2MemMI(instrnsBefore, Reg,getFramePointer(),StackOff,RegType,
addedI.InstrnsBefore.insert(addedI.InstrnsBefore.begin(), scratchReg);
AdICpCC);
if (AdIBef.size() > 0)
if(AdIBefCC) instrnsBefore.insert(instrnsBefore.end(),
addedI.InstrnsBefore.insert(addedI.InstrnsBefore.begin(), AdIAft.begin(), AdIAft.end());
AdIBefCC);
if(DEBUG_RA) {
cerr << "\n!! Inserted caller saving (push) inst for %ccr:";
if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
cerr << "\t" << *AdICpCC;
if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
}
} else {
// for any other register type, just add the push inst
cpReg2MemMI(Reg, getFramePointer(), StackOff, RegType,
PRA.AddedInstrMap[CallMI].InstrnsBefore);
}
//---- Insert code for popping the reg from the stack ---------- //---- Insert code for popping the reg from the stack ----------
if (RegType == IntCCRegType) { // We may need a scratch register to copy the saved value
// from memory. This may itself have to insert code to
// Handle IntCCRegType specially since we cannot directly // free up a scratch register. Any such code should go
// pop %ccr on from the stack // after the save code.
//
// get a free INT register scratchRegType = -1;
int FreeIntReg = scratchReg = -1;
PRA.getUsableUniRegAtMI(PRA.getRegClassByID(IntRegClassID) /* LR->getRegClass()*/, if (this->regTypeNeedsScratchReg(RegType, scratchRegType))
IntRegType, CallMI, &LVSetAft, AdIBefCC, AdIAftCC); { // Find a register not live in the LVSet after CallMI
scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetAft,
if(AdIBefCC) CallMI, AdIBef, AdIAft);
PRA.AddedInstrMap[CallMI].InstrnsAfter.push_back(AdIBefCC); assert(scratchReg != this->getInvalidRegNum());
CallMI->getRegsUsed().insert(scratchReg);
AdICpCC = cpInt2CCRMI(FreeIntReg); }
PRA.AddedInstrMap[CallMI].InstrnsAfter.push_back(AdICpCC);
if (AdIBef.size() > 0)
if(AdIAftCC) instrnsAfter.insert(instrnsAfter.end(),
PRA.AddedInstrMap[CallMI].InstrnsAfter.push_back(AdIAftCC); AdIBef.begin(), AdIBef.end());
if(DEBUG_RA) { cpMem2RegMI(instrnsAfter, getFramePointer(), StackOff,Reg,RegType,
scratchReg);
cerr << "\n!! Inserted caller saving (pop) inst for %ccr:";
if(AdIBefCC) cerr << "\t" << *(AdIBefCC); if (AdIAft.size() > 0)
cerr << "\t" << *AdICpCC; instrnsAfter.insert(instrnsAfter.end(),
if(AdIAftCC) cerr << "\t" << *(AdIAftCC); AdIAft.begin(), AdIAft.end());
}
} else {
// for any other register type, just add the pop inst
cpMem2RegMI(getFramePointer(), StackOff, Reg, RegType,
PRA.AddedInstrMap[CallMI].InstrnsAfter);
}
PushedRegSet.insert(Reg); PushedRegSet.insert(Reg);
if(DEBUG_RA) { if(DEBUG_RA) {
cerr << "\nFor call inst:" << *CallMI; cerr << "\nFor call inst:" << *CallMI;
cerr << " -inserted caller saving instrs:\n\t "; cerr << " -inserted caller saving instrs: Before:\n\t ";
if( RegType == IntCCRegType ) { for_each(instrnsBefore.begin(), instrnsBefore.end(),
if(AdIBefCC) cerr << *AdIBefCC << "\t"; mem_fun(&MachineInstr::dump));
if(AdIAftCC) cerr << *AdIAftCC; cerr << " -and After:\n\t ";
} for_each(instrnsAfter.begin(), instrnsAfter.end(),
else { mem_fun(&MachineInstr::dump));
if(AdIBef) cerr << *AdIBef << "\t";
if(AdIAft) cerr << *AdIAft;
}
} }
} // if not already pushed } // if not already pushed
@ -1356,39 +1445,8 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *CallMI,
} // if there is a LR for Var } // if there is a LR for Var
} // for each value in the LV set after instruction } // for each value in the LV set after instruction
} }
//---------------------------------------------------------------------------
// Copies %ccr into an integer register. IntReg is the UNIFIED register
// number.
//---------------------------------------------------------------------------
MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(unsigned IntReg) const {
MachineInstr * MI = new MachineInstr(RDCCR, 2);
MI->SetMachineOperandReg(0, this->getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
SparcIntCCRegOrder::ccr),
false, true);
MI->SetMachineOperandReg(1, IntReg, true);
return MI;
}
//---------------------------------------------------------------------------
// Copies an integer register into %ccr. IntReg is the UNIFIED register
// number.
//---------------------------------------------------------------------------
MachineInstr *UltraSparcRegInfo::cpInt2CCRMI(unsigned IntReg) const {
MachineInstr *MI = new MachineInstr(WRCCR, 3);
MI->SetMachineOperandReg(0, IntReg, false);
MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
MI->SetMachineOperandReg(2, this->getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID, SparcIntCCRegOrder::ccr),
true, true);
return MI;
}
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
// Print the register assigned to a LR // Print the register assigned to a LR
@ -1434,6 +1492,7 @@ void UltraSparcRegInfo::printReg(const LiveRange *LR) {
// //
// Since instructions are inserted in RegAlloc, this assumes that the // Since instructions are inserted in RegAlloc, this assumes that the
// first operand is the source reg and the last operand is the dest reg. // first operand is the source reg and the last operand is the dest reg.
// It also does not consider operands that are both use and def.
// //
// All the uses are before THE def to a register // All the uses are before THE def to a register
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
@ -1610,7 +1669,7 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
// Save the UReg (%ox) on stack before it's destroyed // Save the UReg (%ox) on stack before it's destroyed
vector<MachineInstr*> mvec; vector<MachineInstr*> mvec;
cpReg2MemMI(UReg, getFramePointer(), StackOff, RegType, mvec); cpReg2MemMI(mvec, UReg, getFramePointer(), StackOff, RegType);
for (vector<MachineInstr*>::iterator MI=mvec.begin(); MI != mvec.end(); ++MI) { for (vector<MachineInstr*>::iterator MI=mvec.begin(); MI != mvec.end(); ++MI) {
OrdIt = OrdVec.insert(OrdIt, *MI); OrdIt = OrdVec.insert(OrdIt, *MI);
++OrdIt; // OrdIt must still point to current instr we processed ++OrdIt; // OrdIt must still point to current instr we processed
@ -1622,7 +1681,7 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
assert(DOp.opIsDef() && "Last operand is not the def"); assert(DOp.opIsDef() && "Last operand is not the def");
const int DReg = DOp.getMachineRegNum(); const int DReg = DOp.getMachineRegNum();
cpMem2RegMI(getFramePointer(), StackOff, DReg, RegType, OrdVec); cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType);
cerr << "\nFixed CIRCULAR references by reordering"; cerr << "\nFixed CIRCULAR references by reordering";