[X86][SSE] LowerScalarImmediateShift - use getTargetConstantBitsFromNode to get immediate data
Don't just attempt to find a splat build vector. First step towards getting rid of all the 32-bit special case code. llvm-svn: 343383
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@ -23422,6 +23422,7 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
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SDLoc dl(Op);
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SDLoc dl(Op);
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SDValue R = Op.getOperand(0);
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SDValue R = Op.getOperand(0);
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SDValue Amt = Op.getOperand(1);
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SDValue Amt = Op.getOperand(1);
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unsigned EltSizeInBits = VT.getScalarSizeInBits();
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unsigned X86Opc = getTargetVShiftUniformOpcode(Op.getOpcode(), false);
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unsigned X86Opc = getTargetVShiftUniformOpcode(Op.getOpcode(), false);
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auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
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auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
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@ -23465,10 +23466,22 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
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};
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};
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// Optimize shl/srl/sra with constant shift amount.
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// Optimize shl/srl/sra with constant shift amount.
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if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
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APInt UndefElts;
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if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
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SmallVector<APInt, 8> EltBits;
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uint64_t ShiftAmt = ShiftConst->getZExtValue();
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if (getTargetConstantBitsFromNode(Amt, EltSizeInBits, UndefElts, EltBits,
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true, false)) {
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int SplatIndex = -1;
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for (int i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
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if (UndefElts[i])
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continue;
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if (0 <= SplatIndex && EltBits[i] != EltBits[SplatIndex])
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return SDValue();
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SplatIndex = i;
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}
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if (SplatIndex < 0)
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return SDValue();
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uint64_t ShiftAmt = EltBits[SplatIndex].getZExtValue();
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if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
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if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
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return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
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return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
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@ -23478,8 +23491,7 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
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Op.getOpcode() == ISD::SRA)
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Op.getOpcode() == ISD::SRA)
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return ArithmeticShiftRight64(ShiftAmt);
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return ArithmeticShiftRight64(ShiftAmt);
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if (VT == MVT::v16i8 ||
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if (VT == MVT::v16i8 || (Subtarget.hasInt256() && VT == MVT::v32i8) ||
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(Subtarget.hasInt256() && VT == MVT::v32i8) ||
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VT == MVT::v64i8) {
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VT == MVT::v64i8) {
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unsigned NumElts = VT.getVectorNumElements();
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unsigned NumElts = VT.getVectorNumElements();
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MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
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MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
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@ -23493,8 +23505,7 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
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SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
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SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
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if (VT.is512BitVector()) {
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if (VT.is512BitVector()) {
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assert(VT == MVT::v64i8 && "Unexpected element type!");
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assert(VT == MVT::v64i8 && "Unexpected element type!");
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SDValue CMP = DAG.getSetCC(dl, MVT::v64i1, Zeros, R,
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SDValue CMP = DAG.getSetCC(dl, MVT::v64i1, Zeros, R, ISD::SETGT);
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ISD::SETGT);
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return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, CMP);
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return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, CMP);
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}
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}
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return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
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return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
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@ -23506,8 +23517,8 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
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if (Op.getOpcode() == ISD::SHL) {
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if (Op.getOpcode() == ISD::SHL) {
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// Make a large shift.
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// Make a large shift.
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SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
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SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT, R,
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R, ShiftAmt, DAG);
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ShiftAmt, DAG);
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SHL = DAG.getBitcast(VT, SHL);
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SHL = DAG.getBitcast(VT, SHL);
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// Zero out the rightmost bits.
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// Zero out the rightmost bits.
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return DAG.getNode(ISD::AND, dl, VT, SHL,
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return DAG.getNode(ISD::AND, dl, VT, SHL,
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@ -23515,8 +23526,8 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
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}
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}
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if (Op.getOpcode() == ISD::SRL) {
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if (Op.getOpcode() == ISD::SRL) {
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// Make a large shift.
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// Make a large shift.
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SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
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SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT, R,
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R, ShiftAmt, DAG);
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ShiftAmt, DAG);
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SRL = DAG.getBitcast(VT, SRL);
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SRL = DAG.getBitcast(VT, SRL);
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// Zero out the leftmost bits.
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// Zero out the leftmost bits.
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return DAG.getNode(ISD::AND, dl, VT, SRL,
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return DAG.getNode(ISD::AND, dl, VT, SRL,
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@ -23534,7 +23545,6 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
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llvm_unreachable("Unknown shift opcode.");
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llvm_unreachable("Unknown shift opcode.");
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}
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}
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}
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}
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}
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// Check cases (mainly 32-bit) where i64 is expanded into high and low parts.
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// Check cases (mainly 32-bit) where i64 is expanded into high and low parts.
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// TODO: Replace constant extraction with getTargetConstantBitsFromNode.
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// TODO: Replace constant extraction with getTargetConstantBitsFromNode.
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