Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt.
Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
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@ -610,7 +610,7 @@ public:
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/// specified instruction is a constant integer. If so, check to see if
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/// specified instruction is a constant integer. If so, check to see if
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/// there are any bits set in the constant that are not demanded. If so,
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/// there are any bits set in the constant that are not demanded. If so,
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/// shrink the constant and return true.
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/// shrink the constant and return true.
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bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
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bool ShrinkDemandedConstant(SDOperand Op, const APInt &Demanded);
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};
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};
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/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
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/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
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@ -621,8 +621,8 @@ public:
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/// KnownZero bits for the expression (used to simplify the caller).
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/// KnownZero bits for the expression (used to simplify the caller).
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/// The KnownZero/One bits may only be accurate for those bits in the
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/// The KnownZero/One bits may only be accurate for those bits in the
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/// DemandedMask.
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/// DemandedMask.
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bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
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bool SimplifyDemandedBits(SDOperand Op, const APInt &DemandedMask,
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uint64_t &KnownZero, uint64_t &KnownOne,
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APInt &KnownZero, APInt &KnownOne,
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TargetLoweringOpt &TLO, unsigned Depth = 0) const;
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TargetLoweringOpt &TLO, unsigned Depth = 0) const;
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/// computeMaskedBitsForTargetNode - Determine which of the bits specified in
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/// computeMaskedBitsForTargetNode - Determine which of the bits specified in
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@ -118,7 +118,12 @@ namespace {
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/// SimplifyDemandedBits - Check the specified integer node value to see if
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/// SimplifyDemandedBits - Check the specified integer node value to see if
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/// it can be simplified or if things it uses can be simplified by bit
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/// it can be simplified or if things it uses can be simplified by bit
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/// propagation. If so, return true.
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/// propagation. If so, return true.
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bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL);
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bool SimplifyDemandedBits(SDOperand Op) {
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APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits());
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return SimplifyDemandedBits(Op, Demanded);
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}
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bool SimplifyDemandedBits(SDOperand Op, const APInt &Demanded);
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bool CombineToPreIndexedLoadStore(SDNode *N);
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bool CombineToPreIndexedLoadStore(SDNode *N);
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bool CombineToPostIndexedLoadStore(SDNode *N);
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bool CombineToPostIndexedLoadStore(SDNode *N);
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@ -534,10 +539,9 @@ SDOperand DAGCombiner::CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
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/// SimplifyDemandedBits - Check the specified integer node value to see if
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/// SimplifyDemandedBits - Check the specified integer node value to see if
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/// it can be simplified or if things it uses can be simplified by bit
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/// it can be simplified or if things it uses can be simplified by bit
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/// propagation. If so, return true.
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/// propagation. If so, return true.
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bool DAGCombiner::SimplifyDemandedBits(SDOperand Op, uint64_t Demanded) {
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bool DAGCombiner::SimplifyDemandedBits(SDOperand Op, const APInt &Demanded) {
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TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize);
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TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize);
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uint64_t KnownZero, KnownOne;
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APInt KnownZero, KnownOne;
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Demanded &= MVT::getIntVTBitMask(Op.getValueType());
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if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
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if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
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return false;
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return false;
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@ -4501,7 +4505,10 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) {
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// Otherwise, see if we can simplify the operation with
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// Otherwise, see if we can simplify the operation with
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// SimplifyDemandedBits, which only works if the value has a single use.
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// SimplifyDemandedBits, which only works if the value has a single use.
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if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getMemoryVT())))
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if (SimplifyDemandedBits(Value,
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APInt::getLowBitsSet(
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Value.getValueSizeInBits(),
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MVT::getSizeInBits(ST->getMemoryVT()))))
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return SDOperand(N, 0);
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return SDOperand(N, 0);
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}
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}
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@ -443,7 +443,7 @@ SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
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/// are any bits set in the constant that are not demanded. If so, shrink the
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/// are any bits set in the constant that are not demanded. If so, shrink the
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/// constant and return true.
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/// constant and return true.
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bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
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bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
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uint64_t Demanded) {
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const APInt &Demanded) {
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// FIXME: ISD::SELECT, ISD::SELECT_CC
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// FIXME: ISD::SELECT, ISD::SELECT_CC
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switch(Op.getOpcode()) {
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switch(Op.getOpcode()) {
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default: break;
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default: break;
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@ -451,10 +451,11 @@ bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
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case ISD::OR:
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case ISD::OR:
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case ISD::XOR:
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case ISD::XOR:
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
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if ((~Demanded & C->getValue()) != 0) {
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if (C->getAPIntValue().intersects(~Demanded)) {
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MVT::ValueType VT = Op.getValueType();
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MVT::ValueType VT = Op.getValueType();
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SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
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SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
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DAG.getConstant(Demanded & C->getValue(),
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DAG.getConstant(Demanded &
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C->getAPIntValue(),
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VT));
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VT));
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return CombineTo(Op, New);
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return CombineTo(Op, New);
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}
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}
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@ -470,17 +471,20 @@ bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
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/// analyze the expression and return a mask of KnownOne and KnownZero bits for
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/// analyze the expression and return a mask of KnownOne and KnownZero bits for
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/// the expression (used to simplify the caller). The KnownZero/One bits may
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/// the expression (used to simplify the caller). The KnownZero/One bits may
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/// only be accurate for those bits in the DemandedMask.
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/// only be accurate for those bits in the DemandedMask.
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bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
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bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
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uint64_t &KnownZero,
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const APInt &DemandedMask,
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uint64_t &KnownOne,
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APInt &KnownZero,
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APInt &KnownOne,
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TargetLoweringOpt &TLO,
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TargetLoweringOpt &TLO,
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unsigned Depth) const {
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unsigned Depth) const {
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KnownZero = KnownOne = 0; // Don't know anything.
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unsigned BitWidth = DemandedMask.getBitWidth();
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assert(Op.getValueSizeInBits() == BitWidth &&
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"Mask size mismatches value type size!");
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APInt NewMask = DemandedMask;
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// Don't know anything.
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KnownZero = KnownOne = APInt(BitWidth, 0);
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// The masks are not wide enough to represent this type! Should use APInt.
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if (Op.getValueType() == MVT::i128)
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return false;
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// Other users may use these bits.
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// Other users may use these bits.
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if (!Op.Val->hasOneUse()) {
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if (!Op.Val->hasOneUse()) {
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if (Depth != 0) {
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if (Depth != 0) {
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@ -490,8 +494,8 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
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return false;
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return false;
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}
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}
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// If this is the root being simplified, allow it to have multiple uses,
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// If this is the root being simplified, allow it to have multiple uses,
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// just set the DemandedMask to all bits.
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// just set the NewMask to all bits.
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DemandedMask = MVT::getIntVTBitMask(Op.getValueType());
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NewMask = APInt::getAllOnesValue(BitWidth);
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} else if (DemandedMask == 0) {
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} else if (DemandedMask == 0) {
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// Not demanding any bits from Op.
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// Not demanding any bits from Op.
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if (Op.getOpcode() != ISD::UNDEF)
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if (Op.getOpcode() != ISD::UNDEF)
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@ -501,12 +505,12 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
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return false;
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return false;
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}
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}
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uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
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APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
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switch (Op.getOpcode()) {
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switch (Op.getOpcode()) {
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case ISD::Constant:
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case ISD::Constant:
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// We know all of the bits for a constant!
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// We know all of the bits for a constant!
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KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask;
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KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
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KnownZero = ~KnownOne & DemandedMask;
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KnownZero = ~KnownOne & NewMask;
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return false; // Don't fall through, will infinitely loop.
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return false; // Don't fall through, will infinitely loop.
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case ISD::AND:
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case ISD::AND:
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// If the RHS is a constant, check to see if the LHS would be zero without
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// If the RHS is a constant, check to see if the LHS would be zero without
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@ -514,38 +518,38 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
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// simplify the LHS, here we're using information from the LHS to simplify
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// simplify the LHS, here we're using information from the LHS to simplify
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// the RHS.
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// the RHS.
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if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t LHSZero, LHSOne;
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APInt LHSZero, LHSOne;
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TLO.DAG.ComputeMaskedBits(Op.getOperand(0), DemandedMask,
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TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
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LHSZero, LHSOne, Depth+1);
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LHSZero, LHSOne, Depth+1);
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// If the LHS already has zeros where RHSC does, this and is dead.
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// If the LHS already has zeros where RHSC does, this and is dead.
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if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask))
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if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
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return TLO.CombineTo(Op, Op.getOperand(0));
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return TLO.CombineTo(Op, Op.getOperand(0));
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// If any of the set bits in the RHS are known zero on the LHS, shrink
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// If any of the set bits in the RHS are known zero on the LHS, shrink
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// the constant.
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// the constant.
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if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask))
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if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
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return true;
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return true;
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}
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}
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if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
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if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
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KnownOne, TLO, Depth+1))
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KnownOne, TLO, Depth+1))
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return true;
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return true;
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero,
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if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
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KnownZero2, KnownOne2, TLO, Depth+1))
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KnownZero2, KnownOne2, TLO, Depth+1))
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return true;
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return true;
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assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
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assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
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// If all of the demanded bits are known one on one side, return the other.
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// If all of the demanded bits are known one on one side, return the other.
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// These bits cannot contribute to the result of the 'and'.
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// These bits cannot contribute to the result of the 'and'.
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if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2))
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if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
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return TLO.CombineTo(Op, Op.getOperand(0));
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return TLO.CombineTo(Op, Op.getOperand(0));
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if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero))
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if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
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return TLO.CombineTo(Op, Op.getOperand(1));
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return TLO.CombineTo(Op, Op.getOperand(1));
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// If all of the demanded bits in the inputs are known zeros, return zero.
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// If all of the demanded bits in the inputs are known zeros, return zero.
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if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask)
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if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
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return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
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return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
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// If the RHS is a constant, see if we can simplify it.
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// If the RHS is a constant, see if we can simplify it.
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if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2))
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if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
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return true;
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return true;
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// Output known-1 bits are only known if set in both the LHS & RHS.
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// Output known-1 bits are only known if set in both the LHS & RHS.
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@ -554,31 +558,29 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
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KnownZero |= KnownZero2;
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KnownZero |= KnownZero2;
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break;
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break;
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case ISD::OR:
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case ISD::OR:
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if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
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if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
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KnownOne, TLO, Depth+1))
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KnownOne, TLO, Depth+1))
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return true;
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return true;
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne,
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if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
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KnownZero2, KnownOne2, TLO, Depth+1))
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KnownZero2, KnownOne2, TLO, Depth+1))
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return true;
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return true;
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assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
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assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
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// If all of the demanded bits are known zero on one side, return the other.
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// If all of the demanded bits are known zero on one side, return the other.
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// These bits cannot contribute to the result of the 'or'.
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// These bits cannot contribute to the result of the 'or'.
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if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2))
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if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
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return TLO.CombineTo(Op, Op.getOperand(0));
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return TLO.CombineTo(Op, Op.getOperand(0));
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if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne))
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if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
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return TLO.CombineTo(Op, Op.getOperand(1));
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return TLO.CombineTo(Op, Op.getOperand(1));
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// If all of the potentially set bits on one side are known to be set on
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// If all of the potentially set bits on one side are known to be set on
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// the other side, just use the 'other' side.
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// the other side, just use the 'other' side.
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if ((DemandedMask & (~KnownZero) & KnownOne2) ==
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if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
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(DemandedMask & (~KnownZero)))
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return TLO.CombineTo(Op, Op.getOperand(0));
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return TLO.CombineTo(Op, Op.getOperand(0));
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if ((DemandedMask & (~KnownZero2) & KnownOne) ==
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if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
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(DemandedMask & (~KnownZero2)))
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return TLO.CombineTo(Op, Op.getOperand(1));
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return TLO.CombineTo(Op, Op.getOperand(1));
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// If the RHS is a constant, see if we can simplify it.
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// If the RHS is a constant, see if we can simplify it.
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if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
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if (TLO.ShrinkDemandedConstant(Op, NewMask))
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return true;
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return true;
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// Output known-0 bits are only known if clear in both the LHS & RHS.
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// Output known-0 bits are only known if clear in both the LHS & RHS.
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@ -587,26 +589,26 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
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KnownOne |= KnownOne2;
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KnownOne |= KnownOne2;
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break;
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break;
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case ISD::XOR:
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case ISD::XOR:
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if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
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if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
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KnownOne, TLO, Depth+1))
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KnownOne, TLO, Depth+1))
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return true;
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return true;
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2,
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if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
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KnownOne2, TLO, Depth+1))
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KnownOne2, TLO, Depth+1))
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return true;
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return true;
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assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
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assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
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// If all of the demanded bits are known zero on one side, return the other.
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// If all of the demanded bits are known zero on one side, return the other.
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// These bits cannot contribute to the result of the 'xor'.
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// These bits cannot contribute to the result of the 'xor'.
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if ((DemandedMask & KnownZero) == DemandedMask)
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if ((KnownZero & NewMask) == NewMask)
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return TLO.CombineTo(Op, Op.getOperand(0));
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return TLO.CombineTo(Op, Op.getOperand(0));
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if ((DemandedMask & KnownZero2) == DemandedMask)
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if ((KnownZero2 & NewMask) == NewMask)
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return TLO.CombineTo(Op, Op.getOperand(1));
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return TLO.CombineTo(Op, Op.getOperand(1));
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// If all of the unknown bits are known to be zero on one side or the other
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// If all of the unknown bits are known to be zero on one side or the other
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// (but not both) turn this into an *inclusive* or.
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// (but not both) turn this into an *inclusive* or.
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||||||
// e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
|
// e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
|
||||||
if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0)
|
if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
|
||||||
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
|
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
|
||||||
Op.getOperand(0),
|
Op.getOperand(0),
|
||||||
Op.getOperand(1)));
|
Op.getOperand(1)));
|
||||||
|
@ -620,10 +622,10 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
|
||||||
// bits on that side are also known to be set on the other side, turn this
|
// bits on that side are also known to be set on the other side, turn this
|
||||||
// into an AND, as we know the bits will be cleared.
|
// into an AND, as we know the bits will be cleared.
|
||||||
// e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
|
// e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
|
||||||
if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known
|
if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
|
||||||
if ((KnownOne & KnownOne2) == KnownOne) {
|
if ((KnownOne & KnownOne2) == KnownOne) {
|
||||||
MVT::ValueType VT = Op.getValueType();
|
MVT::ValueType VT = Op.getValueType();
|
||||||
SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT);
|
SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
|
||||||
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
|
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
|
||||||
ANDC));
|
ANDC));
|
||||||
}
|
}
|
||||||
|
@ -631,29 +633,24 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
|
||||||
|
|
||||||
// If the RHS is a constant, see if we can simplify it.
|
// If the RHS is a constant, see if we can simplify it.
|
||||||
// FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
|
// FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
|
||||||
if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
|
if (TLO.ShrinkDemandedConstant(Op, NewMask))
|
||||||
return true;
|
return true;
|
||||||
|
|
||||||
KnownZero = KnownZeroOut;
|
KnownZero = KnownZeroOut;
|
||||||
KnownOne = KnownOneOut;
|
KnownOne = KnownOneOut;
|
||||||
break;
|
break;
|
||||||
case ISD::SETCC:
|
|
||||||
// If we know the result of a setcc has the top bits zero, use this info.
|
|
||||||
if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
|
|
||||||
KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
|
|
||||||
break;
|
|
||||||
case ISD::SELECT:
|
case ISD::SELECT:
|
||||||
if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero,
|
if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
|
||||||
KnownOne, TLO, Depth+1))
|
KnownOne, TLO, Depth+1))
|
||||||
return true;
|
return true;
|
||||||
if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2,
|
if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
|
||||||
KnownOne2, TLO, Depth+1))
|
KnownOne2, TLO, Depth+1))
|
||||||
return true;
|
return true;
|
||||||
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
||||||
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
|
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
|
||||||
|
|
||||||
// If the operands are constants, see if we can simplify them.
|
// If the operands are constants, see if we can simplify them.
|
||||||
if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
|
if (TLO.ShrinkDemandedConstant(Op, NewMask))
|
||||||
return true;
|
return true;
|
||||||
|
|
||||||
// Only known if known in both the LHS and RHS.
|
// Only known if known in both the LHS and RHS.
|
||||||
|
@ -661,17 +658,17 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
|
||||||
KnownZero &= KnownZero2;
|
KnownZero &= KnownZero2;
|
||||||
break;
|
break;
|
||||||
case ISD::SELECT_CC:
|
case ISD::SELECT_CC:
|
||||||
if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero,
|
if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
|
||||||
KnownOne, TLO, Depth+1))
|
KnownOne, TLO, Depth+1))
|
||||||
return true;
|
return true;
|
||||||
if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2,
|
if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
|
||||||
KnownOne2, TLO, Depth+1))
|
KnownOne2, TLO, Depth+1))
|
||||||
return true;
|
return true;
|
||||||
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
||||||
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
|
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
|
||||||
|
|
||||||
// If the operands are constants, see if we can simplify them.
|
// If the operands are constants, see if we can simplify them.
|
||||||
if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
|
if (TLO.ShrinkDemandedConstant(Op, NewMask))
|
||||||
return true;
|
return true;
|
||||||
|
|
||||||
// Only known if known in both the LHS and RHS.
|
// Only known if known in both the LHS and RHS.
|
||||||
|
@ -683,12 +680,16 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
|
||||||
unsigned ShAmt = SA->getValue();
|
unsigned ShAmt = SA->getValue();
|
||||||
SDOperand InOp = Op.getOperand(0);
|
SDOperand InOp = Op.getOperand(0);
|
||||||
|
|
||||||
|
// If the shift count is an invalid immediate, don't do anything.
|
||||||
|
if (ShAmt >= BitWidth)
|
||||||
|
break;
|
||||||
|
|
||||||
// If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
|
// If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
|
||||||
// single shift. We can do this if the bottom bits (which are shifted
|
// single shift. We can do this if the bottom bits (which are shifted
|
||||||
// out) are never demanded.
|
// out) are never demanded.
|
||||||
if (InOp.getOpcode() == ISD::SRL &&
|
if (InOp.getOpcode() == ISD::SRL &&
|
||||||
isa<ConstantSDNode>(InOp.getOperand(1))) {
|
isa<ConstantSDNode>(InOp.getOperand(1))) {
|
||||||
if (ShAmt && (DemandedMask & ((1ULL << ShAmt)-1)) == 0) {
|
if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
|
||||||
unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
|
unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
|
||||||
unsigned Opc = ISD::SHL;
|
unsigned Opc = ISD::SHL;
|
||||||
int Diff = ShAmt-C1;
|
int Diff = ShAmt-C1;
|
||||||
|
@ -705,28 +706,32 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> ShAmt,
|
if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
|
||||||
KnownZero, KnownOne, TLO, Depth+1))
|
KnownZero, KnownOne, TLO, Depth+1))
|
||||||
return true;
|
return true;
|
||||||
KnownZero <<= SA->getValue();
|
KnownZero <<= SA->getValue();
|
||||||
KnownOne <<= SA->getValue();
|
KnownOne <<= SA->getValue();
|
||||||
KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
|
// low bits known zero.
|
||||||
|
KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getValue());
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case ISD::SRL:
|
case ISD::SRL:
|
||||||
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
|
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
|
||||||
MVT::ValueType VT = Op.getValueType();
|
MVT::ValueType VT = Op.getValueType();
|
||||||
unsigned ShAmt = SA->getValue();
|
unsigned ShAmt = SA->getValue();
|
||||||
uint64_t TypeMask = MVT::getIntVTBitMask(VT);
|
|
||||||
unsigned VTSize = MVT::getSizeInBits(VT);
|
unsigned VTSize = MVT::getSizeInBits(VT);
|
||||||
SDOperand InOp = Op.getOperand(0);
|
SDOperand InOp = Op.getOperand(0);
|
||||||
|
|
||||||
|
// If the shift count is an invalid immediate, don't do anything.
|
||||||
|
if (ShAmt >= BitWidth)
|
||||||
|
break;
|
||||||
|
|
||||||
// If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
|
// If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
|
||||||
// single shift. We can do this if the top bits (which are shifted out)
|
// single shift. We can do this if the top bits (which are shifted out)
|
||||||
// are never demanded.
|
// are never demanded.
|
||||||
if (InOp.getOpcode() == ISD::SHL &&
|
if (InOp.getOpcode() == ISD::SHL &&
|
||||||
isa<ConstantSDNode>(InOp.getOperand(1))) {
|
isa<ConstantSDNode>(InOp.getOperand(1))) {
|
||||||
if (ShAmt && (DemandedMask & (~0ULL << (VTSize-ShAmt))) == 0) {
|
if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
|
||||||
unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
|
unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
|
||||||
unsigned Opc = ISD::SRL;
|
unsigned Opc = ISD::SRL;
|
||||||
int Diff = ShAmt-C1;
|
int Diff = ShAmt-C1;
|
||||||
|
@ -743,17 +748,14 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
|
||||||
}
|
}
|
||||||
|
|
||||||
// Compute the new bits that are at the top now.
|
// Compute the new bits that are at the top now.
|
||||||
if (SimplifyDemandedBits(InOp, (DemandedMask << ShAmt) & TypeMask,
|
if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
|
||||||
KnownZero, KnownOne, TLO, Depth+1))
|
KnownZero, KnownOne, TLO, Depth+1))
|
||||||
return true;
|
return true;
|
||||||
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
||||||
KnownZero &= TypeMask;
|
KnownZero = KnownZero.lshr(ShAmt);
|
||||||
KnownOne &= TypeMask;
|
KnownOne = KnownOne.lshr(ShAmt);
|
||||||
KnownZero >>= ShAmt;
|
|
||||||
KnownOne >>= ShAmt;
|
|
||||||
|
|
||||||
uint64_t HighBits = (1ULL << ShAmt)-1;
|
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
|
||||||
HighBits <<= VTSize - ShAmt;
|
|
||||||
KnownZero |= HighBits; // High bits known zero.
|
KnownZero |= HighBits; // High bits known zero.
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
@ -762,37 +764,34 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
|
||||||
MVT::ValueType VT = Op.getValueType();
|
MVT::ValueType VT = Op.getValueType();
|
||||||
unsigned ShAmt = SA->getValue();
|
unsigned ShAmt = SA->getValue();
|
||||||
|
|
||||||
// Compute the new bits that are at the top now.
|
// If the shift count is an invalid immediate, don't do anything.
|
||||||
uint64_t TypeMask = MVT::getIntVTBitMask(VT);
|
if (ShAmt >= BitWidth)
|
||||||
|
break;
|
||||||
uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask;
|
|
||||||
|
APInt InDemandedMask = (NewMask << ShAmt);
|
||||||
|
|
||||||
// If any of the demanded bits are produced by the sign extension, we also
|
// If any of the demanded bits are produced by the sign extension, we also
|
||||||
// demand the input sign bit.
|
// demand the input sign bit.
|
||||||
uint64_t HighBits = (1ULL << ShAmt)-1;
|
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
|
||||||
HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
|
if (HighBits.intersects(NewMask))
|
||||||
if (HighBits & DemandedMask)
|
InDemandedMask |= APInt::getSignBit(MVT::getSizeInBits(VT));
|
||||||
InDemandedMask |= MVT::getIntVTSignBit(VT);
|
|
||||||
|
|
||||||
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
|
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
|
||||||
KnownZero, KnownOne, TLO, Depth+1))
|
KnownZero, KnownOne, TLO, Depth+1))
|
||||||
return true;
|
return true;
|
||||||
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
||||||
KnownZero &= TypeMask;
|
KnownZero = KnownZero.lshr(ShAmt);
|
||||||
KnownOne &= TypeMask;
|
KnownOne = KnownOne.lshr(ShAmt);
|
||||||
KnownZero >>= ShAmt;
|
|
||||||
KnownOne >>= ShAmt;
|
|
||||||
|
|
||||||
// Handle the sign bits.
|
// Handle the sign bit, adjusted to where it is now in the mask.
|
||||||
uint64_t SignBit = MVT::getIntVTSignBit(VT);
|
APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
|
||||||
SignBit >>= ShAmt; // Adjust to where it is now in the mask.
|
|
||||||
|
|
||||||
// If the input sign bit is known to be zero, or if none of the top bits
|
// If the input sign bit is known to be zero, or if none of the top bits
|
||||||
// are demanded, turn this into an unsigned shift right.
|
// are demanded, turn this into an unsigned shift right.
|
||||||
if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) {
|
if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
|
||||||
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
|
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
|
||||||
Op.getOperand(1)));
|
Op.getOperand(1)));
|
||||||
} else if (KnownOne & SignBit) { // New bits are known one.
|
} else if (KnownOne.intersects(SignBit)) { // New bits are known one.
|
||||||
KnownOne |= HighBits;
|
KnownOne |= HighBits;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -802,14 +801,19 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
|
||||||
|
|
||||||
// Sign extension. Compute the demanded bits in the result that are not
|
// Sign extension. Compute the demanded bits in the result that are not
|
||||||
// present in the input.
|
// present in the input.
|
||||||
uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask;
|
APInt NewBits = APInt::getHighBitsSet(BitWidth,
|
||||||
|
BitWidth - MVT::getSizeInBits(EVT)) &
|
||||||
|
NewMask;
|
||||||
|
|
||||||
// If none of the extended bits are demanded, eliminate the sextinreg.
|
// If none of the extended bits are demanded, eliminate the sextinreg.
|
||||||
if (NewBits == 0)
|
if (NewBits == 0)
|
||||||
return TLO.CombineTo(Op, Op.getOperand(0));
|
return TLO.CombineTo(Op, Op.getOperand(0));
|
||||||
|
|
||||||
uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
|
APInt InSignBit = APInt::getSignBit(MVT::getSizeInBits(EVT));
|
||||||
int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT);
|
InSignBit.zext(BitWidth);
|
||||||
|
APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth,
|
||||||
|
MVT::getSizeInBits(EVT)) &
|
||||||
|
NewMask;
|
||||||
|
|
||||||
// Since the sign extended bits are demanded, we know that the sign
|
// Since the sign extended bits are demanded, we know that the sign
|
||||||
// bit is demanded.
|
// bit is demanded.
|
||||||
|
@ -824,11 +828,11 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
|
||||||
// top bits of the result.
|
// top bits of the result.
|
||||||
|
|
||||||
// If the input sign bit is known zero, convert this into a zero extension.
|
// If the input sign bit is known zero, convert this into a zero extension.
|
||||||
if (KnownZero & InSignBit)
|
if (KnownZero.intersects(InSignBit))
|
||||||
return TLO.CombineTo(Op,
|
return TLO.CombineTo(Op,
|
||||||
TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
|
TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
|
||||||
|
|
||||||
if (KnownOne & InSignBit) { // Input sign bit known set
|
if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
|
||||||
KnownOne |= NewBits;
|
KnownOne |= NewBits;
|
||||||
KnownZero &= ~NewBits;
|
KnownZero &= ~NewBits;
|
||||||
} else { // Input sign bit unknown
|
} else { // Input sign bit unknown
|
||||||
|
@ -837,45 +841,34 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case ISD::CTTZ:
|
|
||||||
case ISD::CTLZ:
|
|
||||||
case ISD::CTPOP: {
|
|
||||||
MVT::ValueType VT = Op.getValueType();
|
|
||||||
unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
|
|
||||||
KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
|
|
||||||
KnownOne = 0;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case ISD::LOAD: {
|
|
||||||
if (ISD::isZEXTLoad(Op.Val)) {
|
|
||||||
LoadSDNode *LD = cast<LoadSDNode>(Op);
|
|
||||||
MVT::ValueType VT = LD->getMemoryVT();
|
|
||||||
KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case ISD::ZERO_EXTEND: {
|
case ISD::ZERO_EXTEND: {
|
||||||
uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
|
unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
|
||||||
|
APInt InMask = NewMask;
|
||||||
|
InMask.trunc(OperandBitWidth);
|
||||||
|
|
||||||
// If none of the top bits are demanded, convert this into an any_extend.
|
// If none of the top bits are demanded, convert this into an any_extend.
|
||||||
uint64_t NewBits = (~InMask) & DemandedMask;
|
APInt NewBits =
|
||||||
if (NewBits == 0)
|
APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
|
||||||
|
if (!NewBits.intersects(NewMask))
|
||||||
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
|
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
|
||||||
Op.getValueType(),
|
Op.getValueType(),
|
||||||
Op.getOperand(0)));
|
Op.getOperand(0)));
|
||||||
|
|
||||||
if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
|
if (SimplifyDemandedBits(Op.getOperand(0), InMask,
|
||||||
KnownZero, KnownOne, TLO, Depth+1))
|
KnownZero, KnownOne, TLO, Depth+1))
|
||||||
return true;
|
return true;
|
||||||
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
||||||
|
KnownZero.zext(BitWidth);
|
||||||
|
KnownOne.zext(BitWidth);
|
||||||
KnownZero |= NewBits;
|
KnownZero |= NewBits;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case ISD::SIGN_EXTEND: {
|
case ISD::SIGN_EXTEND: {
|
||||||
MVT::ValueType InVT = Op.getOperand(0).getValueType();
|
MVT::ValueType InVT = Op.getOperand(0).getValueType();
|
||||||
uint64_t InMask = MVT::getIntVTBitMask(InVT);
|
unsigned InBits = MVT::getSizeInBits(InVT);
|
||||||
uint64_t InSignBit = MVT::getIntVTSignBit(InVT);
|
APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
|
||||||
uint64_t NewBits = (~InMask) & DemandedMask;
|
APInt InSignBit = APInt::getLowBitsSet(BitWidth, InBits);
|
||||||
|
APInt NewBits = ~InMask & NewMask;
|
||||||
|
|
||||||
// If none of the top bits are demanded, convert this into an any_extend.
|
// If none of the top bits are demanded, convert this into an any_extend.
|
||||||
if (NewBits == 0)
|
if (NewBits == 0)
|
||||||
|
@ -884,21 +877,24 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
|
||||||
|
|
||||||
// Since some of the sign extended bits are demanded, we know that the sign
|
// Since some of the sign extended bits are demanded, we know that the sign
|
||||||
// bit is demanded.
|
// bit is demanded.
|
||||||
uint64_t InDemandedBits = DemandedMask & InMask;
|
APInt InDemandedBits = InMask & NewMask;
|
||||||
InDemandedBits |= InSignBit;
|
InDemandedBits |= InSignBit;
|
||||||
|
InDemandedBits.trunc(InBits);
|
||||||
|
|
||||||
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
|
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
|
||||||
KnownOne, TLO, Depth+1))
|
KnownOne, TLO, Depth+1))
|
||||||
return true;
|
return true;
|
||||||
|
KnownZero.zext(BitWidth);
|
||||||
|
KnownOne.zext(BitWidth);
|
||||||
|
|
||||||
// If the sign bit is known zero, convert this to a zero extend.
|
// If the sign bit is known zero, convert this to a zero extend.
|
||||||
if (KnownZero & InSignBit)
|
if (KnownZero.intersects(InSignBit))
|
||||||
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
|
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
|
||||||
Op.getValueType(),
|
Op.getValueType(),
|
||||||
Op.getOperand(0)));
|
Op.getOperand(0)));
|
||||||
|
|
||||||
// If the sign bit is known one, the top bits match.
|
// If the sign bit is known one, the top bits match.
|
||||||
if (KnownOne & InSignBit) {
|
if (KnownOne.intersects(InSignBit)) {
|
||||||
KnownOne |= NewBits;
|
KnownOne |= NewBits;
|
||||||
KnownZero &= ~NewBits;
|
KnownZero &= ~NewBits;
|
||||||
} else { // Otherwise, top bits aren't known.
|
} else { // Otherwise, top bits aren't known.
|
||||||
|
@ -908,36 +904,45 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case ISD::ANY_EXTEND: {
|
case ISD::ANY_EXTEND: {
|
||||||
uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
|
unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
|
||||||
if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
|
APInt InMask = NewMask;
|
||||||
|
InMask.trunc(OperandBitWidth);
|
||||||
|
if (SimplifyDemandedBits(Op.getOperand(0), InMask,
|
||||||
KnownZero, KnownOne, TLO, Depth+1))
|
KnownZero, KnownOne, TLO, Depth+1))
|
||||||
return true;
|
return true;
|
||||||
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
||||||
|
KnownZero.zext(BitWidth);
|
||||||
|
KnownOne.zext(BitWidth);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case ISD::TRUNCATE: {
|
case ISD::TRUNCATE: {
|
||||||
// Simplify the input, using demanded bit information, and compute the known
|
// Simplify the input, using demanded bit information, and compute the known
|
||||||
// zero/one bits live out.
|
// zero/one bits live out.
|
||||||
if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
|
APInt TruncMask = NewMask;
|
||||||
|
TruncMask.zext(Op.getOperand(0).getValueSizeInBits());
|
||||||
|
if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
|
||||||
KnownZero, KnownOne, TLO, Depth+1))
|
KnownZero, KnownOne, TLO, Depth+1))
|
||||||
return true;
|
return true;
|
||||||
|
KnownZero.trunc(BitWidth);
|
||||||
|
KnownOne.trunc(BitWidth);
|
||||||
|
|
||||||
// If the input is only used by this truncate, see if we can shrink it based
|
// If the input is only used by this truncate, see if we can shrink it based
|
||||||
// on the known demanded bits.
|
// on the known demanded bits.
|
||||||
if (Op.getOperand(0).Val->hasOneUse()) {
|
if (Op.getOperand(0).Val->hasOneUse()) {
|
||||||
SDOperand In = Op.getOperand(0);
|
SDOperand In = Op.getOperand(0);
|
||||||
|
unsigned InBitWidth = In.getValueSizeInBits();
|
||||||
switch (In.getOpcode()) {
|
switch (In.getOpcode()) {
|
||||||
default: break;
|
default: break;
|
||||||
case ISD::SRL:
|
case ISD::SRL:
|
||||||
// Shrink SRL by a constant if none of the high bits shifted in are
|
// Shrink SRL by a constant if none of the high bits shifted in are
|
||||||
// demanded.
|
// demanded.
|
||||||
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
|
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
|
||||||
uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType());
|
APInt HighBits = APInt::getHighBitsSet(InBitWidth,
|
||||||
HighBits &= ~MVT::getIntVTBitMask(Op.getValueType());
|
InBitWidth - BitWidth);
|
||||||
HighBits >>= ShAmt->getValue();
|
HighBits = HighBits.lshr(ShAmt->getValue());
|
||||||
|
HighBits.trunc(BitWidth);
|
||||||
|
|
||||||
if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) &&
|
if (ShAmt->getValue() < BitWidth && !(HighBits & NewMask)) {
|
||||||
(DemandedMask & HighBits) == 0) {
|
|
||||||
// None of the shifted in bits are needed. Add a truncate of the
|
// None of the shifted in bits are needed. Add a truncate of the
|
||||||
// shift input, then shift it.
|
// shift input, then shift it.
|
||||||
SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
|
SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
|
||||||
|
@ -952,30 +957,24 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
|
||||||
}
|
}
|
||||||
|
|
||||||
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
||||||
uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
|
|
||||||
KnownZero &= OutMask;
|
|
||||||
KnownOne &= OutMask;
|
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case ISD::AssertZext: {
|
case ISD::AssertZext: {
|
||||||
MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
|
MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
|
||||||
uint64_t InMask = MVT::getIntVTBitMask(VT);
|
APInt InMask = APInt::getLowBitsSet(BitWidth,
|
||||||
if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
|
MVT::getSizeInBits(VT));
|
||||||
|
if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
|
||||||
KnownZero, KnownOne, TLO, Depth+1))
|
KnownZero, KnownOne, TLO, Depth+1))
|
||||||
return true;
|
return true;
|
||||||
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
||||||
KnownZero |= ~InMask & DemandedMask;
|
KnownZero |= ~InMask & NewMask;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case ISD::FGETSIGN:
|
|
||||||
// All bits are zero except the low bit.
|
|
||||||
KnownZero = MVT::getIntVTBitMask(Op.getValueType()) ^ 1;
|
|
||||||
break;
|
|
||||||
case ISD::BIT_CONVERT:
|
case ISD::BIT_CONVERT:
|
||||||
#if 0
|
#if 0
|
||||||
// If this is an FP->Int bitcast and if the sign bit is the only thing that
|
// If this is an FP->Int bitcast and if the sign bit is the only thing that
|
||||||
// is demanded, turn this into a FGETSIGN.
|
// is demanded, turn this into a FGETSIGN.
|
||||||
if (DemandedMask == MVT::getIntVTSignBit(Op.getValueType()) &&
|
if (NewMask == MVT::getIntVTSignBit(Op.getValueType()) &&
|
||||||
MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
|
MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
|
||||||
!MVT::isVector(Op.getOperand(0).getValueType())) {
|
!MVT::isVector(Op.getOperand(0).getValueType())) {
|
||||||
// Only do this xform if FGETSIGN is valid or if before legalize.
|
// Only do this xform if FGETSIGN is valid or if before legalize.
|
||||||
|
@ -998,14 +997,20 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
|
||||||
case ISD::INTRINSIC_WO_CHAIN:
|
case ISD::INTRINSIC_WO_CHAIN:
|
||||||
case ISD::INTRINSIC_W_CHAIN:
|
case ISD::INTRINSIC_W_CHAIN:
|
||||||
case ISD::INTRINSIC_VOID:
|
case ISD::INTRINSIC_VOID:
|
||||||
|
case ISD::CTTZ:
|
||||||
|
case ISD::CTLZ:
|
||||||
|
case ISD::CTPOP:
|
||||||
|
case ISD::LOAD:
|
||||||
|
case ISD::SETCC:
|
||||||
|
case ISD::FGETSIGN:
|
||||||
// Just use ComputeMaskedBits to compute output bits.
|
// Just use ComputeMaskedBits to compute output bits.
|
||||||
TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
|
TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
// If we know the value of all of the demanded bits, return this as a
|
// If we know the value of all of the demanded bits, return this as a
|
||||||
// constant.
|
// constant.
|
||||||
if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
|
if ((NewMask & (KnownZero|KnownOne)) == NewMask)
|
||||||
return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
|
return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
|
||||||
|
|
||||||
return false;
|
return false;
|
||||||
|
|
Loading…
Reference in New Issue