[EarlyCSE] DSE of stores which write back loaded values
Extend EarlyCSE with an additional style of dead store elimination. If we write back a value just read from that memory location, we can eliminate the store under the assumption that the value hasn't changed. I'm implementing this mostly because I noticed the omission when looking at the code. It seemed strange to have InstCombine have a peephole which was more powerful than EarlyCSE. :) Differential Revision: http://reviews.llvm.org/D15397 llvm-svn: 255739
This commit is contained in:
Philip Reames
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e2e332a50e
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ae1f265bf1
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@ -687,6 +687,33 @@ bool EarlyCSE::processNode(DomTreeNode *Node) {
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continue;
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continue;
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}
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}
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// write back DSE - If we write back the same value we just loaded from
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// the same location and haven't passed any intervening writes or ordering
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// operations, we can remove the write. The primary benefit is in allowing
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// the available load table to remain valid and value forward past where
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// the store originally was.
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if (MemInst.isValid() && MemInst.isStore()) {
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LoadValue InVal = AvailableLoads.lookup(MemInst.getPointerOperand());
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if (InVal.Data &&
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InVal.Data == getOrCreateResult(Inst, InVal.Data->getType()) &&
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InVal.Generation == CurrentGeneration &&
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InVal.MatchingId == MemInst.getMatchingId() &&
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// We don't yet handle removing stores with ordering of any kind.
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!MemInst.isVolatile() && MemInst.isUnordered()) {
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assert((!LastStore ||
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ParseMemoryInst(LastStore, TTI).getPointerOperand() ==
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MemInst.getPointerOperand()) &&
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"can't have an intervening store!");
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DEBUG(dbgs() << "EarlyCSE DSE (writeback): " << *Inst << '\n');
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Inst->eraseFromParent();
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Changed = true;
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++NumDSE;
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// We can avoid incrementing the generation count since we were able
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// to eliminate this store.
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continue;
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}
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}
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// Okay, this isn't something we can CSE at all. Check to see if it is
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// Okay, this isn't something we can CSE at all. Check to see if it is
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// something that could modify memory. If so, our available memory values
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// something that could modify memory. If so, our available memory values
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// cannot be used so bump the generation count.
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// cannot be used so bump the generation count.
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@ -203,3 +203,77 @@ define i32 @test12(i1 %B, i32* %P1, i32* %P2) {
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; CHECK: load i32, i32* %P1
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; CHECK: load i32, i32* %P1
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; CHECK: load i32, i32* %P1
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; CHECK: load i32, i32* %P1
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}
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}
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define void @dse1(i32 *%P) {
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; CHECK-LABEL: @dse1
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; CHECK-NOT: store
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%v = load i32, i32* %P
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store i32 %v, i32* %P
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ret void
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}
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define void @dse2(i32 *%P) {
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; CHECK-LABEL: @dse2
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; CHECK-NOT: store
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%v = load atomic i32, i32* %P seq_cst, align 4
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store i32 %v, i32* %P
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ret void
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}
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define void @dse3(i32 *%P) {
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; CHECK-LABEL: @dse3
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; CHECK-NOT: store
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%v = load atomic i32, i32* %P seq_cst, align 4
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store atomic i32 %v, i32* %P unordered, align 4
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ret void
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}
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define i32 @dse4(i32 *%P, i32 *%Q) {
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; CHECK-LABEL: @dse4
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; CHECK-NOT: store
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; CHECK: ret i32 0
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%a = load i32, i32* %Q
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%v = load atomic i32, i32* %P unordered, align 4
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store atomic i32 %v, i32* %P unordered, align 4
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%b = load i32, i32* %Q
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%res = sub i32 %a, %b
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ret i32 %res
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}
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; Note that in this example, %P and %Q could in fact be the same
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; pointer. %v could be different than the value observed for %a
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; and that's okay because we're using relaxed memory ordering.
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; The only guarantee we have to provide is that each of the loads
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; has to observe some value written to that location. We do
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; not have to respect the order in which those writes were done.
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define i32 @dse5(i32 *%P, i32 *%Q) {
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; CHECK-LABEL: @dse5
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; CHECK-NOT: store
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; CHECK: ret i32 0
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%v = load atomic i32, i32* %P unordered, align 4
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%a = load atomic i32, i32* %Q unordered, align 4
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store atomic i32 %v, i32* %P unordered, align 4
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%b = load atomic i32, i32* %Q unordered, align 4
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%res = sub i32 %a, %b
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ret i32 %res
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}
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define void @dse_neg1(i32 *%P) {
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; CHECK-LABEL: @dse_neg1
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; CHECK: store
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%v = load i32, i32* %P
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store i32 5, i32* %P
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ret void
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}
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; Could remove the store, but only if ordering was somehow
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; encoded.
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define void @dse_neg2(i32 *%P) {
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; CHECK-LABEL: @dse_neg2
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; CHECK: store
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%v = load i32, i32* %P
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store atomic i32 %v, i32* %P seq_cst, align 4
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ret void
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}
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