Add code to emulate LDRH (immediate, Thumb) arm instruction.
llvm-svn: 126692
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@ -5871,6 +5871,159 @@ EmulateInstructionARM::EmulateLDRBRegister (ARMEncoding encoding)
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return true;
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}
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// LDRH (immediate, Thumb) calculates an address from a base register value and an immediate offset, loads a
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// halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset,
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// post-indexed, or pre-indexed addressing.
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bool
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EmulateInstructionARM::EmulateLDRHImmediate (ARMEncoding encoding)
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{
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#if 0
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if ConditionPassed() then
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EncodingSpecificOperations(); NullCheckIfThumbEE(n);
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offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
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address = if index then offset_addr else R[n];
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data = MemU[address,2];
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if wback then R[n] = offset_addr;
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if UnalignedSupport() || address<0> = ’0’ then
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R[t] = ZeroExtend(data, 32);
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else // Can only apply before ARMv7
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R[t] = bits(32) UNKNOWN;
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#endif
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bool success = false;
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const uint32_t opcode = OpcodeAsUnsigned (&success);
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if (!success)
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return false;
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if (ConditionPassed())
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{
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uint32_t t;
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uint32_t n;
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uint32_t imm32;
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bool index;
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bool add;
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bool wback;
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// EncodingSpecificOperations(); NullCheckIfThumbEE(n);
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switch (encoding)
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{
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case eEncodingT1:
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// t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:’0’, 32);
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t = Bits32 (opcode, 2, 0);
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n = Bits32 (opcode, 5, 3);
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imm32 = Bits32 (opcode, 10, 6) << 1;
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// index = TRUE; add = TRUE; wback = FALSE;
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index = true;
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add = true;
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wback = false;
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break;
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case eEncodingT2:
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// if Rt == ’1111’ then SEE "Unallocated memory hints";
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// if Rn == ’1111’ then SEE LDRH (literal);
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// t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
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t = Bits32 (opcode, 15, 12);
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n = Bits32 (opcode, 19, 16);
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imm32 = Bits32 (opcode, 11, 0);
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// index = TRUE; add = TRUE; wback = FALSE;
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index = true;
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add = true;
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wback = false;
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// if t == 13 then UNPREDICTABLE;
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if (t == 13)
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return false;
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break;
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case eEncodingT3:
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// if Rn == ’1111’ then SEE LDRH (literal);
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// if Rt == ’1111’ && P == ’1’ && U == ’0’ && W == ’0’ then SEE "Unallocated memory hints";
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// if P == ’1’ && U == ’1’ && W == ’0’ then SEE LDRHT;
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// if P == ’0’ && W == ’0’ then UNDEFINED;
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if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
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return false;
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// t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
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t = Bits32 (opcode, 15, 12);
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n = Bits32 (opcode, 19, 16);
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imm32 = Bits32 (opcode, 7, 0);
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// index = (P == ’1’); add = (U == ’1’); wback = (W == ’1’);
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index = BitIsSet (opcode, 10);
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add = BitIsSet (opcode, 9);
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wback = BitIsSet (opcode, 8);
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// if BadReg(t) || (wback && n == t) then UNPREDICTABLE;
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if (BadReg (t) || (wback && (n == t)))
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return false;
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break;
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default:
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return false;
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}
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// offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
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uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
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if (!success)
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return false;
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addr_t offset_addr;
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addr_t address;
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if (add)
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offset_addr = Rn + imm32;
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else
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offset_addr = Rn - imm32;
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// address = if index then offset_addr else R[n];
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if (index)
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address = offset_addr;
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else
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address = Rn;
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// data = MemU[address,2];
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Register base_reg;
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base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
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EmulateInstruction::Context context;
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context.type = eContextRegisterLoad;
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context.SetRegisterPlusOffset (base_reg, address - Rn);
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uint64_t data = MemURead (context, address, 2, 0, &success);
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if (!success)
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return false;
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// if wback then R[n] = offset_addr;
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if (wback)
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{
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context.type = eContextAdjustBaseRegister;
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context.SetAddress (offset_addr);
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if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
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return false;
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}
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// if UnalignedSupport() || address<0> = ’0’ then
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if (UnalignedSupport () || BitIsClear (address, 0))
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{
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// R[t] = ZeroExtend(data, 32);
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context.type = eContextRegisterLoad;
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context.SetRegisterPlusOffset (base_reg, address - Rn);
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if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
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return false;
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}
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else // Can only apply before ARMv7
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{
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// R[t] = bits(32) UNKNOWN;
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WriteBits32Unknown (t);
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}
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}
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return true;
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}
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// Bitwise Exclusive OR (immediate) performs a bitwise exclusive OR of a register value and an immediate value,
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// and writes the result to the destination register. It can optionally update the condition flags based on
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// the result.
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@ -7481,6 +7634,9 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode)
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{ 0xff7f0000, 0xf81f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>,[...]" },
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{ 0xfffffe00, 0x00005c00, ARMV6T2_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>,[<Rn>,<Rm>]" },
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{ 0xfff00fc0, 0xf8100000, ARMV6T2_ABOVE, eEncodingT2, eSize32,&EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]" },
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{ 0xfffff800, 0x00008800, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>, [<Rn>{,#<imm>}]" },
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{ 0xfff00000, 0xf8b00000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c>.w <Rt>,[<Rn>{,#<imm12>}]" },
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{ 0xfff00800, 0xf8300800, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>,[<Rn>,#+/-<imm8>]{!}" },
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//----------------------------------------------------------------------
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// Store instructions
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@ -600,7 +600,7 @@ protected:
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// A8.6.73 LDRH (immediate, Thumb) - Encoding T1, T2
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bool
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EmulateLDRHImmediateThumb (ARMEncoding encoding);
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EmulateLDRHImmediate (ARMEncoding encoding);
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// A8.6.75 LDRH (literal) - Encoding T1
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bool
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