[AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics
AMDGPU backend errors with "unsupported call to function" upon
encountering a call to llvm.log{,10}.{f16,f32} intrinsics. This patch
adds custom lowering to avoid that error on both R600 and SI.
Reviewers: arsenm, jvesely
Subscribers: tstellar
Differential Revision: https://reviews.llvm.org/D29942
llvm-svn: 319025
This commit is contained in:
Vedran Miletic
parent
4c2c9c3620
commit
ad21f2687d
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@ -13,6 +13,10 @@
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//
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//===----------------------------------------------------------------------===//
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#define AMDGPU_LOG2E_F 1.44269504088896340735992468100189214f
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#define AMDGPU_LN2_F 0.693147180559945309417232121458176568f
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#define AMDGPU_LN10_F 2.30258509299404568401799145468436421f
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#include "AMDGPUISelLowering.h"
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#include "AMDGPU.h"
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#include "AMDGPUCallLowering.h"
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@ -317,6 +321,14 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::FROUND, MVT::f32, Custom);
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setOperationAction(ISD::FROUND, MVT::f64, Custom);
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setOperationAction(ISD::FLOG, MVT::f32, Custom);
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setOperationAction(ISD::FLOG10, MVT::f32, Custom);
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if (Subtarget->has16BitInsts()) {
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setOperationAction(ISD::FLOG, MVT::f16, Custom);
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setOperationAction(ISD::FLOG10, MVT::f16, Custom);
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}
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setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
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setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
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@ -487,6 +499,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::FEXP2, VT, Expand);
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setOperationAction(ISD::FLOG2, VT, Expand);
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setOperationAction(ISD::FREM, VT, Expand);
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setOperationAction(ISD::FLOG, VT, Expand);
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setOperationAction(ISD::FLOG10, VT, Expand);
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setOperationAction(ISD::FPOW, VT, Expand);
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setOperationAction(ISD::FFLOOR, VT, Expand);
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setOperationAction(ISD::FTRUNC, VT, Expand);
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@ -1112,6 +1126,10 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
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case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
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case ISD::FROUND: return LowerFROUND(Op, DAG);
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case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
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case ISD::FLOG:
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return LowerFLOG(Op, DAG, 1 / AMDGPU_LOG2E_F);
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case ISD::FLOG10:
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return LowerFLOG(Op, DAG, AMDGPU_LN2_F / AMDGPU_LN10_F);
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case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
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case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
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case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG);
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@ -2160,6 +2178,18 @@ SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
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}
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SDValue AMDGPUTargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG,
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double Log2BaseInverted) const {
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EVT VT = Op.getValueType();
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SDLoc SL(Op);
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SDValue Operand = Op.getOperand(0);
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SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand);
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SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT);
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return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand);
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}
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static bool isCtlzOpc(unsigned Opc) {
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return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
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}
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@ -57,6 +57,8 @@ protected:
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SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFLOG(SDValue Op, SelectionDAG &Dag,
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double Log2BaseInverted) const;
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SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
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@ -0,0 +1,71 @@
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SIVI -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=SIVI -check-prefix=VIGFX9 -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=VIGFX9 -check-prefix=FUNC %s
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declare half @llvm.log.f16(half %a)
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declare <2 x half> @llvm.log.v2f16(<2 x half> %a)
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; FUNC-LABEL: {{^}}log_f16
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; SI: buffer_load_ushort v[[A_F16_0:[0-9]+]]
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; VI: flat_load_ushort v[[A_F16_0:[0-9]+]]
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; GFX9: global_load_ushort v[[A_F16_0:[0-9]+]]
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; SI: v_mov_b32_e32 v[[A_F32_1:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
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; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
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; SI: v_mul_f32_e32 v[[R_F32_1:[0-9]+]], 0x3f317218, v[[R_F32_0]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_1]]
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; VIGFX9: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
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; VIGFX9: v_mul_f16_e32 v[[R_F16_0]], 0x398c, v[[R_F16_0]]
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; SI: buffer_store_short v[[R_F16_0]], v{{\[[0-9]+:[0-9]+\]}}
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
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; GFX9: global_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
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define void @log_f16(
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half addrspace(1)* %r,
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half addrspace(1)* %a) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%r.val = call half @llvm.log.f16(half %a.val)
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; FUNC-LABEL: {{^}}log_v2f16
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; SI: buffer_load_dword v[[A_F16_0:[0-9]+]]
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; VI: flat_load_dword v[[A_F16_0:[0-9]+]]
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; GFX9: global_load_dword v[[A_F16_0:[0-9]+]]
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; SI: v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x3f317218
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; VIGFX9: v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x398c
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; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_0]]
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; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_F16_0]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
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; SI: v_log_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
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; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
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; SI: v_mul_f32_e32 v[[R_F32_6:[0-9]+]], v[[R_F32_1]], v[[A_F32_2]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_6]]
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; SI: v_mul_f32_e32 v[[R_F32_5:[0-9]+]], v[[R_F32_0]], v[[A_F32_2]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_5]]
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; GFX9: v_log_f16_e32 v[[R_F16_2:[0-9]+]], v[[A_F16_0]]
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; VIGFX9: v_log_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
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; VI: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
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; VI: v_mul_f16_sdwa v[[R_F16_2:[0-9]+]], v[[R_F16_1]], v[[A_F32_2]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
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; GFX9: v_mul_f16_e32 v[[R_F32_3:[0-9]+]], v[[R_F16_2]], v[[A_F32_2]]
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; VIGFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], v[[R_F16_0]], v[[A_F32_2]]
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; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_0]]
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; SI-NOT: v_and_b32_e32
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; SI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]]
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; VI-NOT: v_and_b32_e32
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; VI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_0]], v[[R_F16_2]]
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; GFX9: v_and_b32_e32 v[[R_F32_4:[0-9]+]], 0xffff, v[[R_F32_3]]
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; GFX9: v_lshl_or_b32 v[[R_F32_5:[0-9]+]], v[[R_F32_2]], 16, v[[R_F32_4]]
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; SI: buffer_store_dword v[[R_F32_5]]
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; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
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; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
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define void @log_v2f16(
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<2 x half> addrspace(1)* %r,
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<2 x half> addrspace(1)* %a) {
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entry:
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%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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%r.val = call <2 x half> @llvm.log.v2f16(<2 x half> %a.val)
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store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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ret void
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}
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@ -0,0 +1,89 @@
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; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 --check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}test:
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; EG: LOG_IEEE
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3f317218, v{{[0-9]+}}
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define void @test(float addrspace(1)* %out, float %in) {
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entry:
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%res = call float @llvm.log.f32(float %in)
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store float %res, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}testv2:
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; EG: LOG_IEEE
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; EG: LOG_IEEE
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; FIXME: We should be able to merge these packets together on Cayman so we
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; have a maximum of 4 instructions.
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218
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; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
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define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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entry:
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%res = call <2 x float> @llvm.log.v2f32(<2 x float> %in)
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store <2 x float> %res, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}testv4:
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; EG: LOG_IEEE
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; EG: LOG_IEEE
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; EG: LOG_IEEE
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; EG: LOG_IEEE
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; FIXME: We should be able to merge these packets together on Cayman so we
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; have a maximum of 4 instructions.
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218
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; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
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define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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entry:
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%res = call <4 x float> @llvm.log.v4f32(<4 x float> %in)
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store <4 x float> %res, <4 x float> addrspace(1)* %out
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ret void
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}
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declare float @llvm.log.f32(float) readnone
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declare <2 x float> @llvm.log.v2f32(<2 x float>) readnone
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declare <4 x float> @llvm.log.v4f32(<4 x float>) readnone
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@ -0,0 +1,71 @@
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SIVI -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=SIVI -check-prefix=VIGFX9 -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=VIGFX9 -check-prefix=FUNC %s
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declare half @llvm.log10.f16(half %a)
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declare <2 x half> @llvm.log10.v2f16(<2 x half> %a)
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; GCN-LABEL: {{^}}log10_f16
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; SI: buffer_load_ushort v[[A_F16_0:[0-9]+]]
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; VI: flat_load_ushort v[[A_F16_0:[0-9]+]]
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; GFX9: global_load_ushort v[[A_F16_0:[0-9]+]]
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; SI: v_mov_b32_e32 v[[A_F32_1:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
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; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
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; SI: v_mul_f32_e32 v[[R_F32_1:[0-9]+]], 0x3e9a209a, v[[R_F32_0]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_1]]
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; VIGFX9: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
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; VIGFX9: v_mul_f16_e32 v[[R_F16_0]], 0x34d1, v[[R_F16_0]]
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||||
; SI: buffer_store_short v[[R_F16_0]], v{{\[[0-9]+:[0-9]+\]}}
|
||||
; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
|
||||
; GFX9: global_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
|
||||
define void @log10_f16(
|
||||
half addrspace(1)* %r,
|
||||
half addrspace(1)* %a) {
|
||||
entry:
|
||||
%a.val = load half, half addrspace(1)* %a
|
||||
%r.val = call half @llvm.log10.f16(half %a.val)
|
||||
store half %r.val, half addrspace(1)* %r
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}log10_v2f16
|
||||
; SI: buffer_load_dword v[[A_F16_0:[0-9]+]]
|
||||
; VI: flat_load_dword v[[A_F16_0:[0-9]+]]
|
||||
; GFX9: global_load_dword v[[A_F16_0:[0-9]+]]
|
||||
; SI: v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x3e9a209a
|
||||
; VIGFX9: v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x34d1
|
||||
; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_0]]
|
||||
; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_F16_0]]
|
||||
; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
|
||||
; SI: v_log_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
|
||||
; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
|
||||
; SI: v_mul_f32_e32 v[[R_F32_6:[0-9]+]], v[[R_F32_1]], v[[A_F32_2]]
|
||||
; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_6]]
|
||||
; SI: v_mul_f32_e32 v[[R_F32_5:[0-9]+]], v[[R_F32_0]], v[[A_F32_2]]
|
||||
; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_5]]
|
||||
; GFX9: v_log_f16_e32 v[[R_F16_2:[0-9]+]], v[[A_F16_0]]
|
||||
; VIGFX9: v_log_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
|
||||
; VI: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
|
||||
; VI: v_mul_f16_sdwa v[[R_F16_2:[0-9]+]], v[[R_F16_1]], v[[A_F32_2]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
||||
; GFX9: v_mul_f16_e32 v[[R_F32_3:[0-9]+]], v[[R_F16_2]], v[[A_F32_2]]
|
||||
; VIGFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], v[[R_F16_0]], v[[A_F32_2]]
|
||||
; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_0]]
|
||||
; SI-NOT: v_and_b32_e32
|
||||
; SI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]]
|
||||
; VI-NOT: v_and_b32_e32
|
||||
; VI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_0]], v[[R_F16_2]]
|
||||
; GFX9: v_and_b32_e32 v[[R_F32_4:[0-9]+]], 0xffff, v[[R_F32_3]]
|
||||
; GFX9: v_lshl_or_b32 v[[R_F32_5:[0-9]+]], v[[R_F32_2]], 16, v[[R_F32_4]]
|
||||
; SI: buffer_store_dword v[[R_F32_5]]
|
||||
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
|
||||
; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
|
||||
define void @log10_v2f16(
|
||||
<2 x half> addrspace(1)* %r,
|
||||
<2 x half> addrspace(1)* %a) {
|
||||
entry:
|
||||
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
|
||||
%r.val = call <2 x half> @llvm.log10.v2f16(<2 x half> %a.val)
|
||||
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
|
||||
ret void
|
||||
}
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
|
||||
; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 -check-prefix=FUNC %s
|
||||
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
|
||||
; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
|
||||
|
||||
; FUNC-LABEL: {{^}}test:
|
||||
; EG: LOG_IEEE
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
|
||||
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3e9a209a, v{{[0-9]+}}
|
||||
define void @test(float addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
%res = call float @llvm.log10.f32(float %in)
|
||||
store float %res, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}testv2:
|
||||
; EG: LOG_IEEE
|
||||
; EG: LOG_IEEE
|
||||
; FIXME: We should be able to merge these packets together on Cayman so we
|
||||
; have a maximum of 4 instructions.
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
|
||||
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
|
||||
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
|
||||
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
|
||||
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
|
||||
define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
|
||||
entry:
|
||||
%res = call <2 x float> @llvm.log10.v2f32(<2 x float> %in)
|
||||
store <2 x float> %res, <2 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}testv4:
|
||||
; EG: LOG_IEEE
|
||||
; EG: LOG_IEEE
|
||||
; EG: LOG_IEEE
|
||||
; EG: LOG_IEEE
|
||||
; FIXME: We should be able to merge these packets together on Cayman so we
|
||||
; have a maximum of 4 instructions.
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
|
||||
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
|
||||
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
|
||||
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
|
||||
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
|
||||
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
|
||||
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
|
||||
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
|
||||
define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
|
||||
entry:
|
||||
%res = call <4 x float> @llvm.log10.v4f32(<4 x float> %in)
|
||||
store <4 x float> %res, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
declare float @llvm.log10.f32(float) readnone
|
||||
declare <2 x float> @llvm.log10.v2f32(<2 x float>) readnone
|
||||
declare <4 x float> @llvm.log10.v4f32(<4 x float>) readnone
|
||||
Loading…
Reference in New Issue