[ARM] Add scheduling info for VFMS
The scalar VFMS instructions did not have scheduling information attached (but VFMA did), which was causing assertion failures with the Cortex-A57 scheduling model and -fp-contract=fast. Differential Revision: https://reviews.llvm.org/D34040 llvm-svn: 305064
This commit is contained in:
Oliver Stannard
parent
1b47ff7ee8
commit
ad0973557c
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@ -1958,7 +1958,8 @@ def VFMSD : ADbI<0b11101, 0b10, 1, 0,
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[(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">,
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Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
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Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>,
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Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;
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def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
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(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
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@ -1966,7 +1967,8 @@ def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
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[(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
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SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">,
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>,
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Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines.
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}
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@ -1976,7 +1978,8 @@ def VFMSH : AHbI<0b11101, 0b10, 1, 0,
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IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm",
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[]>,
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RegConstraint<"$Sdin = $Sd">,
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Requires<[HasFullFP16,UseFusedMAC]>;
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Requires<[HasFullFP16,UseFusedMAC]>,
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Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;
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def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
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(VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
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@ -1,5 +1,6 @@
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; REQUIRES: asserts
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-DEFAULT
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null -fp-contract=fast | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FAST
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; Check latencies of vmul/vfma accumulate chains.
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define float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float %f6) {
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@ -14,7 +15,8 @@ define float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float
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; > VMULS read-advanced latency to VMLAS = 0
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; CHECK-SAME: Latency=0
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; CHECK: VMLAS
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; CHECK-DEFAULT: VMLAS
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; CHECK-FAST: VFMAS
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; > VMLAS common latency = 9
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; CHECK: Latency : 9
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; CHECK: Successors:
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@ -22,7 +24,8 @@ define float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float
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; > VMLAS read-advanced latency to the next VMLAS = 4
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; CHECK-SAME: Latency=4
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; CHECK: VMLAS
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; CHECK-DEFAULT: VMLAS
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; CHECK-FAST: VFMAS
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: data
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@ -51,7 +54,8 @@ define <2 x float> @Test2(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2
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; VMULfd read-advanced latency to VMLAfd = 0
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; CHECK-SAME: Latency=0
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; CHECK: VMLAfd
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; CHECK-DEFAULT: VMLAfd
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; CHECK-FAST: VFMAfd
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; > VMLAfd common latency = 9
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; CHECK: Latency : 9
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; CHECK: Successors:
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@ -59,7 +63,8 @@ define <2 x float> @Test2(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2
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; > VMLAfd read-advanced latency to the next VMLAfd = 4
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; CHECK-SAME: Latency=4
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; CHECK: VMLAfd
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; CHECK-DEFAULT: VMLAfd
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; CHECK-FAST: VFMAfd
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: data
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@ -75,3 +80,79 @@ define <2 x float> @Test2(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2
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ret <2 x float> %add2
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}
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define float @Test3(float %f1, float %f2, float %f3, float %f4, float %f5, float %f6) {
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; CHECK: ********** MI Scheduling **********
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; CHECK: Test3:BB#0
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; CHECK: VMULS
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; > VMULS common latency = 5
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; CHECK: Latency : 5
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; CHECK: Successors:
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; CHECK: data
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; > VMULS read-advanced latency to VMLSS = 0
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; CHECK-SAME: Latency=0
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; CHECK-DEFAULT: VMLSS
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; CHECK-FAST: VFMSS
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; > VMLSS common latency = 9
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: data
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; > VMLSS read-advanced latency to the next VMLSS = 4
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; CHECK-SAME: Latency=4
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; CHECK-DEFAULT: VMLSS
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; CHECK-FAST: VFMSS
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: data
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; > VMLSS not-optimized latency to VMOVRS = 9
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; CHECK-SAME: Latency=9
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; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLSS, VMLSS
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%mul1 = fmul float %f1, %f2
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%mul2 = fmul float %f3, %f4
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%mul3 = fmul float %f5, %f6
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%sub1 = fsub float %mul1, %mul2
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%sub2 = fsub float %sub1, %mul3
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ret float %sub2
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}
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; ASIMD form
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define <2 x float> @Test4(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 x float> %f4, <2 x float> %f5, <2 x float> %f6) {
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; CHECK: ********** MI Scheduling **********
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; CHECK: Test4:BB#0
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; CHECK: VMULfd
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; > VMULfd common latency = 5
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; CHECK: Latency : 5
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; CHECK: Successors:
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; CHECK: data
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; VMULfd read-advanced latency to VMLSfd = 0
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; CHECK-SAME: Latency=0
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; CHECK-DEFAULT: VMLSfd
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; CHECK-FAST: VFMSfd
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; > VMLSfd common latency = 9
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: data
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; > VMLSfd read-advanced latency to the next VMLSfd = 4
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; CHECK-SAME: Latency=4
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; CHECK-DEFAULT: VMLSfd
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; CHECK-FAST: VFMSfd
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: data
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; > VMLSfd not-optimized latency to VMOVRRD = 9
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; CHECK-SAME: Latency=9
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; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLSS, VMLSS
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%mul1 = fmul <2 x float> %f1, %f2
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%mul2 = fmul <2 x float> %f3, %f4
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%mul3 = fmul <2 x float> %f5, %f6
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%sub1 = fsub <2 x float> %mul1, %mul2
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%sub2 = fsub <2 x float> %sub1, %mul3
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ret <2 x float> %sub2
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}
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