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Need to special case splat after all. Make the second operand of splat 

vector_shuffle undef.

llvm-svn: 27250
This commit is contained in:
Evan Cheng 2006-03-29 19:02:40 +00:00
parent 5dc61c9076
commit acc336475e
2 changed files with 18 additions and 15 deletions
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16
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -2397,21 +2397,21 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
MVT::ValueType VT = Op.getValueType(); MVT::ValueType VT = Op.getValueType();
unsigned NumElems = PermMask.getNumOperands(); unsigned NumElems = PermMask.getNumOperands();
if (X86::isUNPCKLMask(PermMask.Val) || // Splat && PSHUFD's 2nd vector must be undef.
X86::isUNPCKHMask(PermMask.Val)) if (X86::isSplatMask(PermMask.Val) ||
// Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*. ((MVT::isInteger(VT) && X86::isPSHUFDMask(PermMask.Val)))) {
return SDOperand();
// PSHUFD's 2nd vector must be undef.
if (MVT::isInteger(VT) && X86::isPSHUFDMask(PermMask.Val)) {
if (V2.getOpcode() != ISD::UNDEF) if (V2.getOpcode() != ISD::UNDEF)
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask); DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
return SDOperand(); return SDOperand();
} }
if (X86::isUNPCKLMask(PermMask.Val) ||
X86::isUNPCKHMask(PermMask.Val))
// Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
return SDOperand();
if (NumElems == 2 || if (NumElems == 2 ||
X86::isSplatMask(PermMask.Val) ||
X86::isSHUFPMask(PermMask.Val)) { X86::isSHUFPMask(PermMask.Val)) {
return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG); return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
} }

17
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -58,9 +58,9 @@ def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
return getI8Imm(X86::getShuffleSHUFImmediate(N)); return getI8Imm(X86::getShuffleSHUFImmediate(N));
}]>; }]>;
def v2f64_v2i64_splat_mask : PatLeaf<(build_vector), [{ def SSE_splat_mask : PatLeaf<(build_vector), [{
return X86::isSplatMask(N); return X86::isSplatMask(N);
}]>; }], SHUFFLE_get_shuf_imm>;
def MOVLHPS_shuffle_mask : PatLeaf<(build_vector), [{ def MOVLHPS_shuffle_mask : PatLeaf<(build_vector), [{
return X86::isMOVLHPSMask(N); return X86::isMOVLHPSMask(N);
@ -1375,13 +1375,16 @@ def : Pat<(v16i8 (X86zexts2vec R8:$src)),
(MOVZD128rr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>; (MOVZD128rr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
// Splat v2f64 / v2i64 // Splat v2f64 / v2i64
def : Pat<(vector_shuffle (v2f64 VR128:$src), (v2f64 VR128:$src), def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_mask:$sm),
v2f64_v2i64_splat_mask:$sm), (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
(v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>; def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_mask:$sm),
def : Pat<(vector_shuffle (v2i64 VR128:$src), (v2i64 VR128:$src),
v2f64_v2i64_splat_mask:$sm),
(v2i64 (PUNPCKLQDQrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>; (v2i64 (PUNPCKLQDQrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
// Splat v4f32
def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
(v4f32 (SHUFPSrr VR128:$src, VR128:$src, SSE_splat_mask:$sm))>,
Requires<[HasSSE1]>;
// Shuffle v4i32 if others do not match // Shuffle v4i32 if others do not match
def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2), def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
SHUFP_shuffle_mask:$sm), SHUFP_shuffle_mask:$sm),