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Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and 

FP_TO_XINT.  Necessary for some cleanups I'm working on.  Updated 
from the previous version (r72431) to fix a bug and make some things a 
bit clearer.

llvm-svn: 72445
This commit is contained in:
Eli Friedman 2009-05-27 00:47:34 +00:00
parent de79ea2f51
commit acb851a8c0
2 changed files with 13 additions and 10 deletions
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4
llvm/lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -2304,7 +2304,7 @@ static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
return ExpandLibCall(LC, Op, DAG, false, Dummy, TLI);
}
return SDValue();
return Op;
}
//! Lower ISD::SINT_TO_FP, ISD::UINT_TO_FP for i32
@ -2330,7 +2330,7 @@ static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
return ExpandLibCall(LC, Op, DAG, false, Dummy, TLI);
}
return SDValue();
return Op;
}
//! Lower ISD::SETCC

19
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -4593,12 +4593,14 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
"Unknown SINT_TO_FP to lower!");
// These are really Legal; caller falls through into that case.
// These are really Legal; return the operand so the caller accepts it as
// Legal.
if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
return SDValue();
if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
Subtarget->is64Bit())
return SDValue();
return Op;
if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
Subtarget->is64Bit()) {
return Op;
}
DebugLoc dl = Op.getDebugLoc();
unsigned Size = SrcVT.getSizeInBits()/8;
@ -4793,7 +4795,7 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
MVT SrcVT = N0.getValueType();
if (SrcVT == MVT::i64) {
// We only handle SSE2 f64 target here; caller can handle the rest.
// We only handle SSE2 f64 target here; caller can expand the rest.
if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
return SDValue();
@ -4837,7 +4839,7 @@ FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
return std::make_pair(SDValue(), SDValue());
if (Subtarget->is64Bit() &&
DstTy == MVT::i64 &&
Op.getOperand(0).getValueType() != MVT::f80)
isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
return std::make_pair(SDValue(), SDValue());
// We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
@ -4881,7 +4883,8 @@ FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
SDValue FIST = Vals.first, StackSlot = Vals.second;
if (FIST.getNode() == 0) return SDValue();
// If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
if (FIST.getNode() == 0) return Op;
// Load the result.
return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),