[OpenMP][host runtime] Add initial hybrid CPU support
Detect, through CPUID.1A, and show user different core types through KMP_AFFINITY=verbose mechanism. Offer future runtime optimizations __kmp_is_hybrid_cpu() to know whether running on a hybrid system or not. Differential Revision: https://reviews.llvm.org/D110435
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@ -360,6 +360,7 @@ OmptOutdatedWorkshare "OMPT: Cannot determine workshare type; using the d
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OmpNoAllocator "Allocator %1$s is not available, will use default allocator."
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TopologyGeneric "%1$s: %2$s (%3$d total cores)"
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AffGranularityBad "%1$s: granularity setting: %2$s does not exist in topology. Using granularity=%3$s instead."
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TopologyHybrid "%1$s: hybrid core type detected: %2$d %3$s cores."
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# --- OpenMP errors detected at runtime ---
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#
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@ -1222,7 +1222,8 @@ typedef struct kmp_cpuid {
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typedef struct kmp_cpuinfo_flags_t {
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unsigned sse2 : 1; // 0 if SSE2 instructions are not supported, 1 otherwise.
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unsigned rtm : 1; // 0 if RTM instructions are not supported, 1 otherwise.
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unsigned reserved : 30; // Ensure size of 32 bits
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unsigned hybrid : 1;
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unsigned reserved : 29; // Ensure size of 32 bits
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} kmp_cpuinfo_flags_t;
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typedef struct kmp_cpuinfo {
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@ -2984,6 +2985,9 @@ extern int __kmp_storage_map_verbose_specified;
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#if KMP_ARCH_X86 || KMP_ARCH_X86_64
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extern kmp_cpuinfo_t __kmp_cpuinfo;
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static inline bool __kmp_is_hybrid_cpu() { return __kmp_cpuinfo.flags.hybrid; }
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#else
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static inline bool __kmp_is_hybrid_cpu() { return false; }
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#endif
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extern volatile int __kmp_init_serial;
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@ -123,6 +123,20 @@ const char *__kmp_hw_get_keyword(kmp_hw_t type, bool plural) {
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return ((plural) ? "unknowns" : "unknown");
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}
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const char *__kmp_hw_get_core_type_string(kmp_hw_core_type_t type) {
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switch (type) {
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case KMP_HW_CORE_TYPE_UNKNOWN:
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return "unknown";
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#if KMP_ARCH_X86 || KMP_ARCH_X86_64
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case KMP_HW_CORE_TYPE_ATOM:
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return "Intel Atom(R) processor";
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case KMP_HW_CORE_TYPE_CORE:
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return "Intel(R) Core(TM) processor";
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#endif
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}
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return "unknown";
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}
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////////////////////////////////////////////////////////////////////////////////
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// kmp_hw_thread_t methods
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int kmp_hw_thread_t::compare_ids(const void *a, const void *b) {
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@ -174,6 +188,9 @@ void kmp_hw_thread_t::print() const {
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for (int i = 0; i < depth; ++i) {
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printf("%4d ", ids[i]);
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}
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if (core_type != KMP_HW_CORE_TYPE_UNKNOWN) {
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printf(" (%s)", __kmp_hw_get_core_type_string(core_type));
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}
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printf("\n");
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}
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@ -298,6 +315,7 @@ void kmp_topology_t::_set_last_level_cache() {
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void kmp_topology_t::_gather_enumeration_information() {
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int previous_id[KMP_HW_LAST];
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int max[KMP_HW_LAST];
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int previous_core_id = kmp_hw_thread_t::UNKNOWN_ID;
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for (int i = 0; i < depth; ++i) {
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previous_id[i] = kmp_hw_thread_t::UNKNOWN_ID;
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@ -305,6 +323,12 @@ void kmp_topology_t::_gather_enumeration_information() {
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count[i] = 0;
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ratio[i] = 0;
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}
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if (__kmp_is_hybrid_cpu()) {
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for (int i = 0; i < KMP_HW_MAX_NUM_CORE_TYPES; ++i) {
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core_types_count[i] = 0;
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core_types[i] = KMP_HW_CORE_TYPE_UNKNOWN;
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}
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}
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for (int i = 0; i < num_hw_threads; ++i) {
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kmp_hw_thread_t &hw_thread = hw_threads[i];
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for (int layer = 0; layer < depth; ++layer) {
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@ -326,6 +350,15 @@ void kmp_topology_t::_gather_enumeration_information() {
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for (int layer = 0; layer < depth; ++layer) {
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previous_id[layer] = hw_thread.ids[layer];
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}
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// Figure out the number of each core type for hybrid CPUs
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if (__kmp_is_hybrid_cpu()) {
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int core_level = get_level(KMP_HW_CORE);
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if (core_level != -1) {
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if (hw_thread.ids[core_level] != previous_core_id)
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_increment_core_type(hw_thread.core_type);
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previous_core_id = hw_thread.ids[core_level];
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}
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}
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}
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for (int layer = 0; layer < depth; ++layer) {
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if (max[layer] > ratio[layer])
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@ -478,6 +511,19 @@ void kmp_topology_t::dump() const {
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}
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printf("\n");
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printf("* core_types:\n");
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for (int i = 0; i < KMP_HW_MAX_NUM_CORE_TYPES; ++i) {
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if (core_types[i] != KMP_HW_CORE_TYPE_UNKNOWN) {
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printf(" %d %s core%c\n", core_types_count[i],
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__kmp_hw_get_core_type_string(core_types[i]),
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((core_types_count[i] > 1) ? 's' : ' '));
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} else {
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if (i == 0)
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printf("No hybrid information available\n");
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break;
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}
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}
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printf("* equivalent map:\n");
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KMP_FOREACH_HW_TYPE(i) {
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const char *key = __kmp_hw_get_keyword(i);
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@ -571,6 +617,15 @@ void kmp_topology_t::print(const char *env_var) const {
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}
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KMP_INFORM(TopologyGeneric, env_var, buf.str, ncores);
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if (__kmp_is_hybrid_cpu()) {
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for (int i = 0; i < KMP_HW_MAX_NUM_CORE_TYPES; ++i) {
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if (core_types[i] == KMP_HW_CORE_TYPE_UNKNOWN)
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break;
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KMP_INFORM(TopologyHybrid, env_var, core_types_count[i],
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__kmp_hw_get_core_type_string(core_types[i]));
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}
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}
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if (num_hw_threads <= 0) {
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__kmp_str_buf_free(&buf);
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return;
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@ -585,6 +640,9 @@ void kmp_topology_t::print(const char *env_var) const {
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__kmp_str_buf_print(&buf, "%s ", __kmp_hw_get_catalog_string(type));
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__kmp_str_buf_print(&buf, "%d ", hw_threads[i].ids[level]);
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}
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if (__kmp_is_hybrid_cpu())
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__kmp_str_buf_print(
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&buf, "(%s)", __kmp_hw_get_core_type_string(hw_threads[i].core_type));
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KMP_INFORM(OSProcMapToPack, env_var, hw_threads[i].os_id, buf.str);
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}
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@ -1782,6 +1840,16 @@ static bool __kmp_affinity_create_apicid_map(kmp_i18n_id_t *const msg_id) {
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return true;
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}
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// Hybrid cpu detection using CPUID.1A
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// Thread should be pinned to processor already
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static void __kmp_get_hybrid_info(kmp_hw_core_type_t *type,
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unsigned *native_model_id) {
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kmp_cpuid buf;
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__kmp_x86_cpuid(0x1a, 0, &buf);
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*type = (kmp_hw_core_type_t)__kmp_extract_bits<24, 31>(buf.eax);
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*native_model_id = __kmp_extract_bits<0, 23>(buf.eax);
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}
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// Intel(R) microarchitecture code name Nehalem, Dunnington and later
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// architectures support a newer interface for specifying the x2APIC Ids,
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// based on CPUID.B or CPUID.1F
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@ -2051,6 +2119,13 @@ static bool __kmp_affinity_create_x2apicid_map(kmp_i18n_id_t *const msg_id) {
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hw_thread.ids[idx] >>= my_levels[j - 1].mask_width;
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}
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}
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// Hybrid information
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if (__kmp_is_hybrid_cpu() && highest_leaf >= 0x1a) {
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kmp_hw_core_type_t type;
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unsigned native_model_id;
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__kmp_get_hybrid_info(&type, &native_model_id);
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hw_thread.core_type = type;
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}
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hw_thread_index++;
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}
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KMP_ASSERT(hw_thread_index > 0);
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@ -598,6 +598,17 @@ class KMPNativeAffinity : public KMPAffinity {
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#endif /* KMP_OS_WINDOWS */
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#endif /* KMP_AFFINITY_SUPPORTED */
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typedef enum kmp_hw_core_type_t {
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KMP_HW_CORE_TYPE_UNKNOWN = 0x0,
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#if KMP_ARCH_X86 || KMP_ARCH_X86_64
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KMP_HW_CORE_TYPE_ATOM = 0x20,
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KMP_HW_CORE_TYPE_CORE = 0x40,
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KMP_HW_MAX_NUM_CORE_TYPES = 3,
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#else
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KMP_HW_MAX_NUM_CORE_TYPES = 1,
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#endif
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} kmp_hw_core_type_t;
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class kmp_hw_thread_t {
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public:
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static const int UNKNOWN_ID = -1;
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int sub_ids[KMP_HW_LAST];
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bool leader;
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int os_id;
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kmp_hw_core_type_t core_type;
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void print() const;
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void clear() {
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for (int i = 0; i < (int)KMP_HW_LAST; ++i)
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ids[i] = UNKNOWN_ID;
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leader = false;
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core_type = KMP_HW_CORE_TYPE_UNKNOWN;
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}
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};
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// Storage containing the absolute number of each topology layer
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int *count;
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// Storage containing the core types and the number of
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// each core type for hybrid processors
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kmp_hw_core_type_t core_types[KMP_HW_MAX_NUM_CORE_TYPES];
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int core_types_count[KMP_HW_MAX_NUM_CORE_TYPES];
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// The hardware threads array
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// hw_threads is num_hw_threads long
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// Each hw_thread's ids and sub_ids are depth deep
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// Set the last level cache equivalent type
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void _set_last_level_cache();
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// Increments the number of cores of type 'type'
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void _increment_core_type(kmp_hw_core_type_t type) {
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for (int i = 0; i < KMP_HW_MAX_NUM_CORE_TYPES; ++i) {
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if (core_types[i] == KMP_HW_CORE_TYPE_UNKNOWN) {
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core_types[i] = type;
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core_types_count[i] = 1;
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break;
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} else if (core_types[i] == type) {
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core_types_count[i]++;
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break;
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}
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}
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}
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public:
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// Force use of allocate()/deallocate()
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kmp_topology_t() = delete;
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@ -248,13 +248,19 @@ void __kmp_query_cpuid(kmp_cpuinfo_t *p) {
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}
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#endif
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p->flags.rtm = 0;
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p->flags.hybrid = 0;
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if (max_arg > 7) {
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/* RTM bit CPUID.07:EBX, bit 11 */
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/* HYRBID bit CPUID.07:EDX, bit 15 */
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__kmp_x86_cpuid(7, 0, &buf);
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p->flags.rtm = (buf.ebx >> 11) & 1;
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p->flags.hybrid = (buf.edx >> 15) & 1;
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if (p->flags.rtm) {
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KA_TRACE(trace_level, (" RTM"));
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}
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if (p->flags.hybrid) {
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KA_TRACE(trace_level, (" HYBRID"));
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}
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}
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}
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