LivePhysRegs: Rework constructor + documentation; NFC

- Take reference instead of pointer to a TRI that cannot be nullptr.
- Improve documentation comments.

llvm-svn: 304038
This commit is contained in:
Matthias Braun 2017-05-26 21:51:00 +00:00
parent d35ebd44e0
commit ac4307c41e
11 changed files with 31 additions and 32 deletions

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@ -44,33 +44,32 @@ class MachineOperand;
class MachineRegisterInfo; class MachineRegisterInfo;
class raw_ostream; class raw_ostream;
/// \brief A set of live physical registers with functions to track liveness /// \brief A set of physical registers with utility functions to track liveness
/// when walking backward/forward through a basic block. /// when walking backward/forward through a basic block.
class LivePhysRegs { class LivePhysRegs {
const TargetRegisterInfo *TRI = nullptr; const TargetRegisterInfo *TRI = nullptr;
SparseSet<unsigned> LiveRegs; SparseSet<unsigned> LiveRegs;
public: public:
/// Constructs a new empty LivePhysRegs set. /// Constructs an unitialized set. init() needs to be called to initialize it.
LivePhysRegs() = default; LivePhysRegs() = default;
/// Constructs and initialize an empty LivePhysRegs set. /// Constructs and initializes an empty set.
LivePhysRegs(const TargetRegisterInfo *TRI) : TRI(TRI) { LivePhysRegs(const TargetRegisterInfo &TRI) : TRI(&TRI) {
assert(TRI && "Invalid TargetRegisterInfo pointer."); LiveRegs.setUniverse(TRI.getNumRegs());
LiveRegs.setUniverse(TRI->getNumRegs());
} }
LivePhysRegs(const LivePhysRegs&) = delete; LivePhysRegs(const LivePhysRegs&) = delete;
LivePhysRegs &operator=(const LivePhysRegs&) = delete; LivePhysRegs &operator=(const LivePhysRegs&) = delete;
/// Clear and initialize the LivePhysRegs set. /// (re-)initializes and clears the set.
void init(const TargetRegisterInfo &TRI) { void init(const TargetRegisterInfo &TRI) {
this->TRI = &TRI; this->TRI = &TRI;
LiveRegs.clear(); LiveRegs.clear();
LiveRegs.setUniverse(TRI.getNumRegs()); LiveRegs.setUniverse(TRI.getNumRegs());
} }
/// Clears the LivePhysRegs set. /// Clears the set.
void clear() { LiveRegs.clear(); } void clear() { LiveRegs.clear(); }
/// Returns true if the set is empty. /// Returns true if the set is empty.
@ -134,7 +133,7 @@ public:
/// callee saved registers. /// callee saved registers.
void addLiveOuts(const MachineBasicBlock &MBB); void addLiveOuts(const MachineBasicBlock &MBB);
/// Like addLiveOuts() but does not add pristine registers/callee saved /// Adds all live-out registers of basic block \p MBB but skips pristine
/// registers. /// registers.
void addLiveOutsNoPristines(const MachineBasicBlock &MBB); void addLiveOutsNoPristines(const MachineBasicBlock &MBB);
@ -160,7 +159,7 @@ inline raw_ostream &operator<<(raw_ostream &OS, const LivePhysRegs& LR) {
return OS; return OS;
} }
/// \brief Compute the live-in list for \p MBB assuming all of its successors /// \brief Computes the live-in list for \p MBB assuming all of its successors
/// live-in lists are up-to-date. Uses the given LivePhysReg instance \p /// live-in lists are up-to-date. Uses the given LivePhysReg instance \p
/// LiveRegs; This is just here to avoid repeated heap allocations when calling /// LiveRegs; This is just here to avoid repeated heap allocations when calling
/// this multiple times in a pass. /// this multiple times in a pass.

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@ -601,7 +601,7 @@ bool AArch64ExpandPseudo::expandCMP_SWAP(
MachineOperand &Desired = MI.getOperand(3); MachineOperand &Desired = MI.getOperand(3);
MachineOperand &New = MI.getOperand(4); MachineOperand &New = MI.getOperand(4);
LivePhysRegs LiveRegs(&TII->getRegisterInfo()); LivePhysRegs LiveRegs(TII->getRegisterInfo());
LiveRegs.addLiveOuts(MBB); LiveRegs.addLiveOuts(MBB);
for (auto I = std::prev(MBB.end()); I != MBBI; --I) for (auto I = std::prev(MBB.end()); I != MBBI; --I)
LiveRegs.stepBackward(*I); LiveRegs.stepBackward(*I);
@ -677,7 +677,7 @@ bool AArch64ExpandPseudo::expandCMP_SWAP_128(
MachineOperand &NewLo = MI.getOperand(6); MachineOperand &NewLo = MI.getOperand(6);
MachineOperand &NewHi = MI.getOperand(7); MachineOperand &NewHi = MI.getOperand(7);
LivePhysRegs LiveRegs(&TII->getRegisterInfo()); LivePhysRegs LiveRegs(TII->getRegisterInfo());
LiveRegs.addLiveOuts(MBB); LiveRegs.addLiveOuts(MBB);
for (auto I = std::prev(MBB.end()); I != MBBI; --I) for (auto I = std::prev(MBB.end()); I != MBBI; --I)
LiveRegs.stepBackward(*I); LiveRegs.stepBackward(*I);

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@ -267,12 +267,12 @@ static unsigned findScratchNonCalleeSaveRegister(MachineBasicBlock *MBB) {
return AArch64::X9; return AArch64::X9;
const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>(); const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>();
const AArch64RegisterInfo *TRI = Subtarget.getRegisterInfo(); const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo();
LivePhysRegs LiveRegs(TRI); LivePhysRegs LiveRegs(TRI);
LiveRegs.addLiveIns(*MBB); LiveRegs.addLiveIns(*MBB);
// Mark callee saved registers as used so we will not choose them. // Mark callee saved registers as used so we will not choose them.
const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(MF); const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(MF);
for (unsigned i = 0; CSRegs[i]; ++i) for (unsigned i = 0; CSRegs[i]; ++i)
LiveRegs.addReg(CSRegs[i]); LiveRegs.addReg(CSRegs[i]);

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@ -779,7 +779,7 @@ bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
MachineOperand &Desired = MI.getOperand(3); MachineOperand &Desired = MI.getOperand(3);
MachineOperand &New = MI.getOperand(4); MachineOperand &New = MI.getOperand(4);
LivePhysRegs LiveRegs(&TII->getRegisterInfo()); LivePhysRegs LiveRegs(TII->getRegisterInfo());
LiveRegs.addLiveOuts(MBB); LiveRegs.addLiveOuts(MBB);
for (auto I = std::prev(MBB.end()); I != MBBI; --I) for (auto I = std::prev(MBB.end()); I != MBBI; --I)
LiveRegs.stepBackward(*I); LiveRegs.stepBackward(*I);
@ -903,7 +903,7 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
unsigned DesiredLo = TRI->getSubReg(Desired.getReg(), ARM::gsub_0); unsigned DesiredLo = TRI->getSubReg(Desired.getReg(), ARM::gsub_0);
unsigned DesiredHi = TRI->getSubReg(Desired.getReg(), ARM::gsub_1); unsigned DesiredHi = TRI->getSubReg(Desired.getReg(), ARM::gsub_1);
LivePhysRegs LiveRegs(&TII->getRegisterInfo()); LivePhysRegs LiveRegs(TII->getRegisterInfo());
LiveRegs.addLiveOuts(MBB); LiveRegs.addLiveOuts(MBB);
for (auto I = std::prev(MBB.end()); I != MBBI; --I) for (auto I = std::prev(MBB.end()); I != MBBI; --I)
LiveRegs.stepBackward(*I); LiveRegs.stepBackward(*I);

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@ -535,14 +535,14 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
// Look for a temporary register to use. // Look for a temporary register to use.
// First, compute the liveness information. // First, compute the liveness information.
LivePhysRegs UsedRegs(STI.getRegisterInfo()); const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
LivePhysRegs UsedRegs(TRI);
UsedRegs.addLiveOuts(MBB); UsedRegs.addLiveOuts(MBB);
// The semantic of pristines changed recently and now, // The semantic of pristines changed recently and now,
// the callee-saved registers that are touched in the function // the callee-saved registers that are touched in the function
// are not part of the pristines set anymore. // are not part of the pristines set anymore.
// Add those callee-saved now. // Add those callee-saved now.
const TargetRegisterInfo *TRI = STI.getRegisterInfo(); const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
for (unsigned i = 0; CSRegs[i]; ++i) for (unsigned i = 0; CSRegs[i]; ++i)
UsedRegs.addReg(CSRegs[i]); UsedRegs.addReg(CSRegs[i]);
@ -561,12 +561,12 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
// And some temporary register, just in case. // And some temporary register, just in case.
unsigned TemporaryReg = 0; unsigned TemporaryReg = 0;
BitVector PopFriendly = BitVector PopFriendly =
TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::tGPRRegClassID)); TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID));
assert(PopFriendly.any() && "No allocatable pop-friendly register?!"); assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
// Rebuild the GPRs from the high registers because they are removed // Rebuild the GPRs from the high registers because they are removed
// form the GPR reg class for thumb1. // form the GPR reg class for thumb1.
BitVector GPRsNoLRSP = BitVector GPRsNoLRSP =
TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::hGPRRegClassID)); TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID));
GPRsNoLRSP |= PopFriendly; GPRsNoLRSP |= PopFriendly;
GPRsNoLRSP.reset(ARM::LR); GPRsNoLRSP.reset(ARM::LR);
GPRsNoLRSP.reset(ARM::SP); GPRsNoLRSP.reset(ARM::SP);

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@ -1657,7 +1657,7 @@ bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
// defined. From the point of view of the liveness tracking, it is ok to // defined. From the point of view of the liveness tracking, it is ok to
// store it as a whole, but if we break it up we may end up storing a // store it as a whole, but if we break it up we may end up storing a
// register that is entirely undefined. // register that is entirely undefined.
LivePhysRegs LPR(&HRI); LivePhysRegs LPR(HRI);
LPR.addLiveIns(B); LPR.addLiveIns(B);
SmallVector<std::pair<unsigned, const MachineOperand*>,2> Clobbers; SmallVector<std::pair<unsigned, const MachineOperand*>,2> Clobbers;
for (auto R = B.begin(); R != It; ++R) { for (auto R = B.begin(); R != It; ++R) {

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@ -1254,7 +1254,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
const MachineOperand &Op1 = MI.getOperand(1); const MachineOperand &Op1 = MI.getOperand(1);
const MachineOperand &Op2 = MI.getOperand(2); const MachineOperand &Op2 = MI.getOperand(2);
const MachineOperand &Op3 = MI.getOperand(3); const MachineOperand &Op3 = MI.getOperand(3);
LivePhysRegs LiveAtMI(&HRI); LivePhysRegs LiveAtMI(HRI);
getLiveRegsAt(LiveAtMI, MI); getLiveRegsAt(LiveAtMI, MI);
bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg()); bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
if (Op0.getReg() != Op2.getReg()) { if (Op0.getReg() != Op2.getReg()) {
@ -1283,7 +1283,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
MachineOperand &Op1 = MI.getOperand(1); MachineOperand &Op1 = MI.getOperand(1);
MachineOperand &Op2 = MI.getOperand(2); MachineOperand &Op2 = MI.getOperand(2);
MachineOperand &Op3 = MI.getOperand(3); MachineOperand &Op3 = MI.getOperand(3);
LivePhysRegs LiveAtMI(&HRI); LivePhysRegs LiveAtMI(HRI);
getLiveRegsAt(LiveAtMI, MI); getLiveRegsAt(LiveAtMI, MI);
bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg()); bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());

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@ -339,7 +339,7 @@ void PPCExpandISEL::reorganizeBlockLayout(BlockISELList &BIL,
// Note: Cannot use stepBackward instead since we are using the Reg // Note: Cannot use stepBackward instead since we are using the Reg
// liveness state at the end of MBB (liveOut of MBB) as the liveIn for // liveness state at the end of MBB (liveOut of MBB) as the liveIn for
// NewSuccessor. Otherwise, will cause cyclic dependence. // NewSuccessor. Otherwise, will cause cyclic dependence.
LivePhysRegs LPR(MF->getSubtarget<PPCSubtarget>().getRegisterInfo()); LivePhysRegs LPR(*MF->getSubtarget<PPCSubtarget>().getRegisterInfo());
SmallVector<std::pair<unsigned, const MachineOperand *>, 2> Clobbers; SmallVector<std::pair<unsigned, const MachineOperand *>, 2> Clobbers;
for (MachineInstr &MI : *MBB) for (MachineInstr &MI : *MBB)
LPR.stepForward(MI, Clobbers); LPR.stepForward(MI, Clobbers);

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@ -74,7 +74,7 @@ bool SystemZExpandPseudo::expandLOCRMux(MachineBasicBlock &MBB,
unsigned CCValid = MI.getOperand(3).getImm(); unsigned CCValid = MI.getOperand(3).getImm();
unsigned CCMask = MI.getOperand(4).getImm(); unsigned CCMask = MI.getOperand(4).getImm();
LivePhysRegs LiveRegs(&TII->getRegisterInfo()); LivePhysRegs LiveRegs(TII->getRegisterInfo());
LiveRegs.addLiveOuts(MBB); LiveRegs.addLiveOuts(MBB);
for (auto I = std::prev(MBB.end()); I != MBBI; --I) for (auto I = std::prev(MBB.end()); I != MBBI; --I)
LiveRegs.stepBackward(*I); LiveRegs.stepBackward(*I);

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@ -1655,8 +1655,8 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
} }
void FPS::setKillFlags(MachineBasicBlock &MBB) const { void FPS::setKillFlags(MachineBasicBlock &MBB) const {
const TargetRegisterInfo *TRI = const TargetRegisterInfo &TRI =
MBB.getParent()->getSubtarget().getRegisterInfo(); *MBB.getParent()->getSubtarget().getRegisterInfo();
LivePhysRegs LPR(TRI); LivePhysRegs LPR(TRI);
LPR.addLiveOuts(MBB); LPR.addLiveOuts(MBB);

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@ -5936,7 +5936,7 @@ void X86InstrInfo::replaceBranchWithTailCall(
// Add implicit uses and defs of all live regs potentially clobbered by the // Add implicit uses and defs of all live regs potentially clobbered by the
// call. This way they still appear live across the call. // call. This way they still appear live across the call.
LivePhysRegs LiveRegs(&getRegisterInfo()); LivePhysRegs LiveRegs(getRegisterInfo());
LiveRegs.addLiveOuts(MBB); LiveRegs.addLiveOuts(MBB);
SmallVector<std::pair<unsigned, const MachineOperand *>, 8> Clobbers; SmallVector<std::pair<unsigned, const MachineOperand *>, 8> Clobbers;
LiveRegs.stepForward(*MIB, Clobbers); LiveRegs.stepForward(*MIB, Clobbers);
@ -6551,9 +6551,9 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
// first frame index. // first frame index.
// See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment. // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
const TargetRegisterInfo *TRI = &getRegisterInfo(); const TargetRegisterInfo &TRI = getRegisterInfo();
MachineBasicBlock::LivenessQueryResult LQR = MachineBasicBlock::LivenessQueryResult LQR =
MBB.computeRegisterLiveness(TRI, AX, MI); MBB.computeRegisterLiveness(&TRI, AX, MI);
// We do not want to save and restore AX if we do not have to. // We do not want to save and restore AX if we do not have to.
// Moreover, if we do so whereas AX is dead, we would need to set // Moreover, if we do so whereas AX is dead, we would need to set
// an undef flag on the use of AX, otherwise the verifier will // an undef flag on the use of AX, otherwise the verifier will
@ -6570,7 +6570,7 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
} }
// AX contains the top most register in the aliasing hierarchy. // AX contains the top most register in the aliasing hierarchy.
// It may not be live, but one of its aliases may be. // It may not be live, but one of its aliases may be.
for (MCRegAliasIterator AI(AX, TRI, true); for (MCRegAliasIterator AI(AX, &TRI, true);
AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI) AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
: MachineBasicBlock::LQR_Dead; : MachineBasicBlock::LQR_Dead;