[AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma
See bugs 35494 and 35559: https://bugs.llvm.org/show_bug.cgi?id=35494 https://bugs.llvm.org/show_bug.cgi?id=35559 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41007 llvm-svn: 320375
This commit is contained in:
Dmitry Preobrazhensky
parent
f3436d7dab
commit
ac2b02643b
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@ -2578,6 +2578,25 @@ bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
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bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
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unsigned RegNo) const {
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for (MCRegAliasIterator R(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, &MRI, true);
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R.isValid(); ++R) {
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if (*R == RegNo)
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return isGFX9();
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}
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switch (RegNo) {
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case AMDGPU::TBA:
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case AMDGPU::TBA_LO:
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case AMDGPU::TBA_HI:
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case AMDGPU::TMA:
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case AMDGPU::TMA_LO:
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case AMDGPU::TMA_HI:
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return !isGFX9();
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default:
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break;
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}
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if (isCI())
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return true;
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@ -250,7 +250,7 @@ DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
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int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
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if (SDst != -1) {
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// VOPC - insert VCC register as sdst
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insertNamedMCOperand(MI, MCOperand::createReg(AMDGPU::VCC),
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insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
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AMDGPU::OpName::sdst);
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} else {
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// VOP1/2 - insert omod if present in instruction
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@ -277,7 +277,7 @@ MCOperand AMDGPUDisassembler::errOperand(unsigned V,
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inline
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MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
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return MCOperand::createReg(RegId);
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return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
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}
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inline
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@ -571,6 +571,15 @@ unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
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}
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}
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int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
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using namespace AMDGPU::EncValues;
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unsigned TTmpMin = isGFX9() ? TTMP_GFX9_MIN : TTMP_VI_MIN;
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unsigned TTmpMax = isGFX9() ? TTMP_GFX9_MAX : TTMP_VI_MAX;
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return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
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}
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MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
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using namespace AMDGPU::EncValues;
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@ -583,8 +592,10 @@ MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) c
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assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
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return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
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}
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if (TTMP_MIN <= Val && Val <= TTMP_MAX) {
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return createSRegOperand(getTtmpClassId(Width), Val - TTMP_MIN);
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int TTmpIdx = getTTmpIdx(Val);
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if (TTmpIdx >= 0) {
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return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
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}
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if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
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@ -612,17 +623,17 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
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using namespace AMDGPU;
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switch (Val) {
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case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI));
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case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI));
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case 102: return createRegOperand(FLAT_SCR_LO);
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case 103: return createRegOperand(FLAT_SCR_HI);
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// ToDo: no support for xnack_mask_lo/_hi register
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case 104:
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case 105: break;
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case 106: return createRegOperand(VCC_LO);
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case 107: return createRegOperand(VCC_HI);
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case 108: return createRegOperand(TBA_LO);
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case 109: return createRegOperand(TBA_HI);
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case 110: return createRegOperand(TMA_LO);
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case 111: return createRegOperand(TMA_HI);
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case 108: assert(!isGFX9()); return createRegOperand(TBA_LO);
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case 109: assert(!isGFX9()); return createRegOperand(TBA_HI);
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case 110: assert(!isGFX9()); return createRegOperand(TMA_LO);
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case 111: assert(!isGFX9()); return createRegOperand(TMA_HI);
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case 124: return createRegOperand(M0);
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case 126: return createRegOperand(EXEC_LO);
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case 127: return createRegOperand(EXEC_HI);
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@ -645,10 +656,10 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
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using namespace AMDGPU;
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switch (Val) {
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case 102: return createRegOperand(getMCReg(FLAT_SCR, STI));
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case 102: return createRegOperand(FLAT_SCR);
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case 106: return createRegOperand(VCC);
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case 108: return createRegOperand(TBA);
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case 110: return createRegOperand(TMA);
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case 108: assert(!isGFX9()); return createRegOperand(TBA);
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case 110: assert(!isGFX9()); return createRegOperand(TMA);
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case 126: return createRegOperand(EXEC);
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default: break;
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}
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@ -672,6 +683,11 @@ MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
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return createSRegOperand(getSgprClassId(Width),
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Val - SDWA9EncValues::SRC_SGPR_MIN);
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}
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if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
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Val <= SDWA9EncValues::SRC_TTMP_MAX) {
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return createSRegOperand(getTtmpClassId(Width),
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Val - SDWA9EncValues::SRC_TTMP_MIN);
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}
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return decodeSpecialReg32(Val - SDWA9EncValues::SRC_SGPR_MIN);
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} else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
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@ -695,7 +711,11 @@ MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
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"SDWAVopcDst should be present only on GFX9");
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if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
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Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
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if (Val > AMDGPU::EncValues::SGPR_MAX) {
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int TTmpIdx = getTTmpIdx(Val);
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if (TTmpIdx >= 0) {
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return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx);
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} else if (Val > AMDGPU::EncValues::SGPR_MAX) {
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return decodeSpecialReg64(Val);
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} else {
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return createSRegOperand(getSgprClassId(OPW64), Val);
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@ -705,6 +725,14 @@ MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
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}
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}
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bool AMDGPUDisassembler::isVI() const {
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return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
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}
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bool AMDGPUDisassembler::isGFX9() const {
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return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
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}
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//===----------------------------------------------------------------------===//
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// AMDGPUSymbolizer
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//===----------------------------------------------------------------------===//
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@ -111,6 +111,11 @@ public:
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MCOperand decodeSDWASrc16(unsigned Val) const;
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MCOperand decodeSDWASrc32(unsigned Val) const;
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MCOperand decodeSDWAVopcDst(unsigned Val) const;
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int getTTmpIdx(unsigned Val) const;
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bool isVI() const;
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bool isGFX9() const;
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};
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//===----------------------------------------------------------------------===//
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@ -344,16 +344,6 @@ void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
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} else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(RegNo)) {
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O << 's';
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NumRegs = 16;
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} else if (MRI.getRegClass(AMDGPU::TTMP_64RegClassID).contains(RegNo)) {
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O << "ttmp";
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NumRegs = 2;
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// Trap temps start at offset 112. TODO: Get this from tablegen.
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RegIdx -= 112;
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} else if (MRI.getRegClass(AMDGPU::TTMP_128RegClassID).contains(RegNo)) {
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O << "ttmp";
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NumRegs = 4;
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// Trap temps start at offset 112. TODO: Get this from tablegen.
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RegIdx -= 112;
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} else {
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O << getRegisterName(RegNo);
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return;
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@ -194,8 +194,10 @@ namespace EncValues { // Encoding values of enum9/8/7 operands
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enum {
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SGPR_MIN = 0,
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SGPR_MAX = 101,
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TTMP_MIN = 112,
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TTMP_MAX = 123,
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TTMP_VI_MIN = 112,
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TTMP_VI_MAX = 123,
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TTMP_GFX9_MIN = 108,
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TTMP_GFX9_MAX = 123,
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INLINE_INTEGER_C_MIN = 128,
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INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
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INLINE_INTEGER_C_MAX = 208,
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@ -368,6 +370,8 @@ enum SDWA9EncValues{
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SRC_VGPR_MAX = 255,
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SRC_SGPR_MIN = 256,
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SRC_SGPR_MAX = 357,
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SRC_TTMP_MIN = 364,
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SRC_TTMP_MAX = 379,
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};
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} // namespace SDWA
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@ -172,6 +172,8 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP10_TTMP11);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP12_TTMP13);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP14_TTMP15);
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const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
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@ -77,18 +77,11 @@ def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]>,
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let HWEncoding = 110;
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}
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def TTMP0 : SIReg <"ttmp0", 112>;
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def TTMP1 : SIReg <"ttmp1", 113>;
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def TTMP2 : SIReg <"ttmp2", 114>;
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def TTMP3 : SIReg <"ttmp3", 115>;
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def TTMP4 : SIReg <"ttmp4", 116>;
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def TTMP5 : SIReg <"ttmp5", 117>;
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def TTMP6 : SIReg <"ttmp6", 118>;
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def TTMP7 : SIReg <"ttmp7", 119>;
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def TTMP8 : SIReg <"ttmp8", 120>;
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def TTMP9 : SIReg <"ttmp9", 121>;
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def TTMP10 : SIReg <"ttmp10", 122>;
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def TTMP11 : SIReg <"ttmp11", 123>;
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foreach Index = 0-15 in {
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def TTMP#Index#_vi : SIReg<"ttmp"#Index, !add(112, Index)>;
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def TTMP#Index#_gfx9 : SIReg<"ttmp"#Index, !add(108, Index)>;
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def TTMP#Index : SIReg<"", 0>;
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}
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multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> {
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def _ci : SIReg<n, ci_e>;
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@ -192,7 +185,7 @@ def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
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// Trap handler TMP 32-bit registers
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def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32,
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(add (sequence "TTMP%u", 0, 11))> {
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(add (sequence "TTMP%u", 0, 15))> {
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let isAllocatable = 0;
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}
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@ -208,6 +201,36 @@ def TTMP_128Regs : RegisterTuples<[sub0, sub1, sub2, sub3],
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(add (decimate (shl TTMP_32, 2), 4)),
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(add (decimate (shl TTMP_32, 3), 4))]>;
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class TmpRegTuples <string tgt,
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bit Is64Bit,
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int Index0,
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int Index1 = !add(Index0, 1),
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int Index2 = !add(Index0, !if(Is64Bit, 1, 2)),
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int Index3 = !add(Index0, !if(Is64Bit, 1, 3)),
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string name = "ttmp["#Index0#":"#Index3#"]",
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Register r0 = !cast<Register>("TTMP"#Index0#tgt),
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Register r1 = !cast<Register>("TTMP"#Index1#tgt),
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Register r2 = !cast<Register>("TTMP"#Index2#tgt),
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Register r3 = !cast<Register>("TTMP"#Index3#tgt)> :
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RegisterWithSubRegs<name, !if(Is64Bit, [r0, r1], [r0, r1, r2, r3])> {
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let SubRegIndices = !if(Is64Bit, [sub0, sub1], [sub0, sub1, sub2, sub3]);
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let HWEncoding = r0.HWEncoding;
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}
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foreach Index = {0, 2, 4, 6, 8, 10, 12, 14} in {
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def TTMP#Index#_TTMP#!add(Index,1)#_vi : TmpRegTuples<"_vi", 1, Index>;
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def TTMP#Index#_TTMP#!add(Index,1)#_gfx9 : TmpRegTuples<"_gfx9", 1, Index>;
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}
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foreach Index = {0, 4, 8, 12} in {
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def TTMP#Index#_TTMP#!add(Index,1)#
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_TTMP#!add(Index,2)#
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_TTMP#!add(Index,3)#_vi : TmpRegTuples<"_vi", 0, Index>;
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def TTMP#Index#_TTMP#!add(Index,1)#
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_TTMP#!add(Index,2)#
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_TTMP#!add(Index,3)#_gfx9 : TmpRegTuples<"_gfx9", 0, Index>;
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}
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// VGPR 32-bit registers
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// i16/f16 only on VI+
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def VGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
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@ -569,44 +569,68 @@ bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
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return false;
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}
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#define MAP_REG2REG \
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using namespace AMDGPU; \
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switch(Reg) { \
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default: return Reg; \
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CASE_CI_VI(FLAT_SCR) \
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CASE_CI_VI(FLAT_SCR_LO) \
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CASE_CI_VI(FLAT_SCR_HI) \
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CASE_VI_GFX9(TTMP0) \
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CASE_VI_GFX9(TTMP1) \
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CASE_VI_GFX9(TTMP2) \
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CASE_VI_GFX9(TTMP3) \
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CASE_VI_GFX9(TTMP4) \
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CASE_VI_GFX9(TTMP5) \
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CASE_VI_GFX9(TTMP6) \
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CASE_VI_GFX9(TTMP7) \
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CASE_VI_GFX9(TTMP8) \
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CASE_VI_GFX9(TTMP9) \
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CASE_VI_GFX9(TTMP10) \
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CASE_VI_GFX9(TTMP11) \
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CASE_VI_GFX9(TTMP12) \
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CASE_VI_GFX9(TTMP13) \
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CASE_VI_GFX9(TTMP14) \
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CASE_VI_GFX9(TTMP15) \
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CASE_VI_GFX9(TTMP0_TTMP1) \
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CASE_VI_GFX9(TTMP2_TTMP3) \
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CASE_VI_GFX9(TTMP4_TTMP5) \
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CASE_VI_GFX9(TTMP6_TTMP7) \
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CASE_VI_GFX9(TTMP8_TTMP9) \
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CASE_VI_GFX9(TTMP10_TTMP11) \
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CASE_VI_GFX9(TTMP12_TTMP13) \
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CASE_VI_GFX9(TTMP14_TTMP15) \
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CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3) \
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CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7) \
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CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11) \
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CASE_VI_GFX9(TTMP12_TTMP13_TTMP14_TTMP15) \
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}
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#define CASE_CI_VI(node) \
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assert(!isSI(STI)); \
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case node: return isCI(STI) ? node##_ci : node##_vi;
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#define CASE_VI_GFX9(node) \
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case node: return isGFX9(STI) ? node##_gfx9 : node##_vi;
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unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
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switch(Reg) {
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default: break;
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case AMDGPU::FLAT_SCR:
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assert(!isSI(STI));
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return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi;
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case AMDGPU::FLAT_SCR_LO:
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assert(!isSI(STI));
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return isCI(STI) ? AMDGPU::FLAT_SCR_LO_ci : AMDGPU::FLAT_SCR_LO_vi;
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case AMDGPU::FLAT_SCR_HI:
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assert(!isSI(STI));
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return isCI(STI) ? AMDGPU::FLAT_SCR_HI_ci : AMDGPU::FLAT_SCR_HI_vi;
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}
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return Reg;
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MAP_REG2REG
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}
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#undef CASE_CI_VI
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#undef CASE_VI_GFX9
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#define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
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#define CASE_VI_GFX9(node) case node##_vi: case node##_gfx9: return node;
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unsigned mc2PseudoReg(unsigned Reg) {
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switch (Reg) {
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case AMDGPU::FLAT_SCR_ci:
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case AMDGPU::FLAT_SCR_vi:
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return FLAT_SCR;
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case AMDGPU::FLAT_SCR_LO_ci:
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case AMDGPU::FLAT_SCR_LO_vi:
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return AMDGPU::FLAT_SCR_LO;
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case AMDGPU::FLAT_SCR_HI_ci:
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case AMDGPU::FLAT_SCR_HI_vi:
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return AMDGPU::FLAT_SCR_HI;
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|
||||
default:
|
||||
return Reg;
|
||||
}
|
||||
MAP_REG2REG
|
||||
}
|
||||
|
||||
#undef CASE_CI_VI
|
||||
#undef CASE_VI_GFX9
|
||||
#undef MAP_REG2REG
|
||||
|
||||
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
|
||||
assert(OpNo < Desc.NumOperands);
|
||||
unsigned OpType = Desc.OpInfo[OpNo].OperandType;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx901 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX9 %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX9 %s
|
||||
|
||||
v_pk_add_f16 v1, -17, v2
|
||||
// GFX9: :19: error: invalid operand for instruction
|
||||
|
|
|
|||
|
|
@ -1,6 +1,12 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
|
||||
// RUN: llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
|
||||
// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
|
||||
// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
|
||||
|
||||
// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOGFX9
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Trap Handler related - 32 bit registers
|
||||
|
|
@ -9,90 +15,130 @@
|
|||
s_add_u32 ttmp0, ttmp0, 4
|
||||
// SICI: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x70,0x84,0x70,0x80]
|
||||
// VI: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x70,0x84,0x70,0x80]
|
||||
// GFX9: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x6c,0x84,0x6c,0x80]
|
||||
|
||||
s_add_u32 ttmp4, 8, ttmp4
|
||||
// SICI: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x74,0x74,0x80]
|
||||
// VI: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x74,0x74,0x80]
|
||||
// GXF9: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x70,0x70,0x80]
|
||||
|
||||
s_add_u32 ttmp4, ttmp4, 0x00000100
|
||||
// SICI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
|
||||
// VI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
|
||||
// GXF9: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x70,0xff,0x70,0x80,0x00,0x01,0x00,0x00]
|
||||
|
||||
s_add_u32 ttmp4, ttmp4, 4
|
||||
// SICI: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x74,0x84,0x74,0x80]
|
||||
// VI: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x74,0x84,0x74,0x80]
|
||||
// GXF9: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x70,0x84,0x70,0x80]
|
||||
|
||||
s_add_u32 ttmp4, ttmp8, ttmp4
|
||||
// SICI: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x78,0x74,0x74,0x80]
|
||||
// VI: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x78,0x74,0x74,0x80]
|
||||
// GXF9: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x74,0x70,0x70,0x80]
|
||||
|
||||
s_and_b32 ttmp10, ttmp8, 0x00000080
|
||||
// SICI: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x78,0xff,0x7a,0x87,0x80,0x00,0x00,0x00]
|
||||
// VI: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x78,0xff,0x7a,0x86,0x80,0x00,0x00,0x00]
|
||||
// GXF9: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x74,0xff,0x74,0x86,0x80,0x00,0x00,0x00]
|
||||
|
||||
s_and_b32 ttmp9, tma_hi, 0x0000ffff
|
||||
// SICI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x87,0xff,0xff,0x00,0x00]
|
||||
// VI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x86,0xff,0xff,0x00,0x00]
|
||||
// NOGFX9: error: not a valid operand
|
||||
|
||||
s_and_b32 ttmp9, ttmp9, 0x000001ff
|
||||
// SICI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x87,0xff,0x01,0x00,0x00]
|
||||
// VI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x86,0xff,0x01,0x00,0x00]
|
||||
// GXF9: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x75,0xff,0x75,0x86,0xff,0x01,0x00,0x00]
|
||||
|
||||
s_and_b32 ttmp9, tma_lo, 0xffff0000
|
||||
// SICI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x87,0x00,0x00,0xff,0xff]
|
||||
// VI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x86,0x00,0x00,0xff,0xff]
|
||||
// NOGFX9: error: not a valid operand
|
||||
|
||||
s_and_b32 ttmp9, ttmp9, ttmp8
|
||||
// SICI: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x79,0x78,0x79,0x87]
|
||||
// VI: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x79,0x78,0x79,0x86]
|
||||
// GXF9: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x75,0x78,0x75,0x86]
|
||||
|
||||
s_and_b32 ttmp8, ttmp1, 0x01000000
|
||||
// SICI: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x87,0x00,0x00,0x00,0x01]
|
||||
// VI: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x86,0x00,0x00,0x00,0x01]
|
||||
// GXF9: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x6d,0xff,0x74,0x86,0x00,0x00,0x00,0x01]
|
||||
|
||||
s_cmp_eq_i32 ttmp8, 0
|
||||
// SICI: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x78,0x80,0x00,0xbf]
|
||||
// VI: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x78,0x80,0x00,0xbf]
|
||||
// GXF9: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x74,0x80,0x00,0xbf]
|
||||
|
||||
s_cmp_eq_i32 ttmp8, 0x000000fe
|
||||
// SICI: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
|
||||
// VI: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
|
||||
// GXF9: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x74,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
|
||||
|
||||
s_lshr_b32 ttmp8, ttmp8, 12
|
||||
// SICI: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x78,0x8c,0x78,0x90]
|
||||
// VI: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x78,0x8c,0x78,0x8f]
|
||||
// GXF9: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x74,0x8c,0x74,0x8f]
|
||||
|
||||
v_mov_b32_e32 v1, ttmp8
|
||||
// SICI: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x78,0x02,0x02,0x7e]
|
||||
// VI: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x78,0x02,0x02,0x7e]
|
||||
// GXF9: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x74,0x02,0x02,0x7e]
|
||||
|
||||
s_mov_b32 m0, ttmp8
|
||||
// SICI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x03,0xfc,0xbe]
|
||||
// VI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x00,0xfc,0xbe]
|
||||
// GXF9: s_mov_b32 m0, ttmp8 ; encoding: [0x74,0x00,0xfc,0xbe]
|
||||
|
||||
s_mov_b32 ttmp10, 0
|
||||
// SICI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x03,0xfa,0xbe]
|
||||
// VI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xfa,0xbe]
|
||||
// GXF9: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xf6,0xbe]
|
||||
|
||||
s_mov_b32 ttmp11, 0x01024fac
|
||||
// SICI: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x03,0xfb,0xbe,0xac,0x4f,0x02,0x01]
|
||||
// VI: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xfb,0xbe,0xac,0x4f,0x02,0x01]
|
||||
// GXF9: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xf7,0xbe,0xac,0x4f,0x02,0x01]
|
||||
|
||||
s_mov_b32 ttmp8, m0
|
||||
// SICI: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x03,0xf8,0xbe]
|
||||
// VI: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x00,0xf8,0xbe]
|
||||
// GXF9: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x00,0xf4,0xbe]
|
||||
|
||||
s_mov_b32 ttmp8, tma_lo
|
||||
// SICI: s_mov_b32 ttmp8, tma_lo ; encoding: [0x6e,0x03,0xf8,0xbe]
|
||||
// VI: s_mov_b32 ttmp8, tma_lo ; encoding: [0x6e,0x00,0xf8,0xbe]
|
||||
// NOGFX9: error: not a valid operand
|
||||
|
||||
s_mul_i32 ttmp8, 0x00000324, ttmp8
|
||||
// SICI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x93,0x24,0x03,0x00,0x00]
|
||||
// VI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x92,0x24,0x03,0x00,0x00]
|
||||
// GXF9: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x74,0x74,0x92,0x24,0x03,0x00,0x00]
|
||||
|
||||
s_or_b32 ttmp9, ttmp9, 0x00280000
|
||||
// SICI: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x79,0xff,0x79,0x88,0x00,0x00,0x28,0x00]
|
||||
// VI: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x79,0xff,0x79,0x87,0x00,0x00,0x28,0x00]
|
||||
// GXF9: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x75,0xff,0x75,0x87,0x00,0x00,0x28,0x00]
|
||||
|
||||
// ttmp12..ttmp15 (GFX9 only)
|
||||
|
||||
s_add_u32 ttmp0, ttmp12, 4
|
||||
// NOSICIVI: error: not a valid operand
|
||||
// GFX9: s_add_u32 ttmp0, ttmp12, 4 ; encoding: [0x78,0x84,0x6c,0x80]
|
||||
|
||||
s_add_u32 ttmp0, ttmp13, 4
|
||||
// NOSICIVI: error: not a valid operand
|
||||
// GFX9: s_add_u32 ttmp0, ttmp13, 4 ; encoding: [0x79,0x84,0x6c,0x80]
|
||||
|
||||
s_add_u32 ttmp0, ttmp14, 4
|
||||
// NOSICIVI: error: not a valid operand
|
||||
// GFX9: s_add_u32 ttmp0, ttmp14, 4 ; encoding: [0x7a,0x84,0x6c,0x80]
|
||||
|
||||
s_add_u32 ttmp0, ttmp15, 4
|
||||
// NOSICIVI: error: not a valid operand
|
||||
// GFX9: s_add_u32 ttmp0, ttmp15, 4 ; encoding: [0x7b,0x84,0x6c,0x80]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Trap Handler related - Pairs and quadruples of registers
|
||||
|
|
@ -101,31 +147,47 @@ s_or_b32 ttmp9, ttmp9, 0x00280000
|
|||
s_mov_b64 ttmp[4:5], exec
|
||||
// SICI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x04,0xf4,0xbe]
|
||||
// VI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf4,0xbe]
|
||||
// GFX9: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf0,0xbe]
|
||||
|
||||
s_mov_b64 [ttmp4,ttmp5], exec
|
||||
// SICI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x04,0xf4,0xbe]
|
||||
// VI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf4,0xbe]
|
||||
// GFX9: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf0,0xbe]
|
||||
|
||||
s_mov_b64 exec, [ttmp4,ttmp5]
|
||||
// SICI: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x74,0x04,0xfe,0xbe]
|
||||
// VI: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x74,0x01,0xfe,0xbe]
|
||||
// GFX9: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x70,0x01,0xfe,0xbe]
|
||||
|
||||
s_mov_b64 tba, ttmp[4:5]
|
||||
// SICI: s_mov_b64 tba, ttmp[4:5] ; encoding: [0x74,0x04,0xec,0xbe]
|
||||
// VI: s_mov_b64 tba, ttmp[4:5] ; encoding: [0x74,0x01,0xec,0xbe]
|
||||
// NOGFX9: error: not a valid operand
|
||||
|
||||
s_mov_b64 ttmp[4:5], tba
|
||||
// SICI: s_mov_b64 ttmp[4:5], tba ; encoding: [0x6c,0x04,0xf4,0xbe]
|
||||
// VI: s_mov_b64 ttmp[4:5], tba ; encoding: [0x6c,0x01,0xf4,0xbe]
|
||||
// NOGFX9: error: not a valid operand
|
||||
|
||||
s_mov_b64 tma, ttmp[4:5]
|
||||
// SICI: s_mov_b64 tma, ttmp[4:5] ; encoding: [0x74,0x04,0xee,0xbe]
|
||||
// VI: s_mov_b64 tma, ttmp[4:5] ; encoding: [0x74,0x01,0xee,0xbe]
|
||||
// NOGFX9: error: not a valid operand
|
||||
|
||||
s_mov_b64 ttmp[4:5], tma
|
||||
// SICI: s_mov_b64 ttmp[4:5], tma ; encoding: [0x6e,0x04,0xf4,0xbe]
|
||||
// VI: s_mov_b64 ttmp[4:5], tma ; encoding: [0x6e,0x01,0xf4,0xbe]
|
||||
// NOGFX9: error: not a valid operand
|
||||
|
||||
// ttmp12..ttmp15 (GFX9 only)
|
||||
|
||||
s_mov_b64 ttmp[12:13], exec
|
||||
// NOSICIVI: error: not a valid operand
|
||||
// GFX9: s_mov_b64 ttmp[12:13], exec ; encoding: [0x7e,0x01,0xf8,0xbe]
|
||||
|
||||
s_mov_b64 ttmp[14:15], exec
|
||||
// NOSICIVI: error: not a valid operand
|
||||
// GFX9: s_mov_b64 ttmp[14:15], exec ; encoding: [0x7e,0x01,0xfa,0xbe]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Trap Handler related - Some specific instructions
|
||||
|
|
@ -134,11 +196,20 @@ s_mov_b64 ttmp[4:5], tma
|
|||
s_setpc_b64 [ttmp2,ttmp3]
|
||||
// SICI: s_setpc_b64 ttmp[2:3] ; encoding: [0x72,0x20,0x80,0xbe]
|
||||
// VI: s_setpc_b64 ttmp[2:3] ; encoding: [0x72,0x1d,0x80,0xbe]
|
||||
// GFX9: s_setpc_b64 ttmp[2:3] ; encoding: [0x6e,0x1d,0x80,0xbe]
|
||||
|
||||
v_readfirstlane_b32 ttmp8, v1
|
||||
// SICI: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xf0,0x7e]
|
||||
// VI: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xf0,0x7e]
|
||||
// GFX9: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xe8,0x7e]
|
||||
|
||||
buffer_atomic_inc v1, off, ttmp[8:11], 56 glc
|
||||
// SICI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0xf0,0xe0,0x00,0x01,0x1e,0xb8]
|
||||
// VI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
|
||||
// GFX9: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1d,0xb8]
|
||||
|
||||
// ttmp12..ttmp15 (GFX9 only)
|
||||
|
||||
buffer_atomic_inc v1, off, ttmp[12:15], 56 glc
|
||||
// NOSICIVI: error: not a valid operand
|
||||
// GFX9: buffer_atomic_inc v1, off, ttmp[12:15], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx901 -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
|
||||
|
||||
|
|
|
|||
|
|
@ -692,6 +692,11 @@ v_mov_b32 v1, s2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
|
|||
// GFX9: v_mov_b32_sdwa v1, exec dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x7e,0x10,0x86,0x06]
|
||||
v_mov_b32 v1, exec dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
|
||||
|
||||
// NOSICI: error:
|
||||
// NOVI: error:
|
||||
// GFX9: v_mov_b32_sdwa v1, ttmp12 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x78,0x10,0x86,0x06]
|
||||
v_mov_b32_sdwa v1, ttmp12 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
|
||||
|
||||
// NOSICI: error:
|
||||
// NOVI: error:
|
||||
// GFX9: v_add_f32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x06,0x85,0x02]
|
||||
|
|
@ -707,6 +712,16 @@ v_add_f32 v0, v0, s22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_s
|
|||
// NO: invalid operand (violates constant bus restrictions)
|
||||
v_add_f32 v0, exec, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
|
||||
|
||||
// NOSICI: error:
|
||||
// NOVI: error:
|
||||
// NO: error: not a valid operand
|
||||
v_add_f32 v0, v1, tba_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
|
||||
|
||||
// NOSICI: error:
|
||||
// NOVI: error:
|
||||
// NO: error: not a valid operand
|
||||
v_add_f32 v0, v1, tma_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
|
||||
|
||||
// NOSICI: error:
|
||||
// NOVI: error:
|
||||
// GFX9: v_cmp_eq_f32_sdwa vcc, s1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x85,0x02]
|
||||
|
|
@ -717,6 +732,26 @@ v_cmp_eq_f32_sdwa vcc, s1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
|
|||
// GFX9: v_cmp_eq_f32_sdwa vcc, v1, s22 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x2c,0x84,0x7c,0x01,0x00,0x05,0x82]
|
||||
v_cmp_eq_f32_sdwa vcc, v1, s22 src0_sel:WORD_1 src1_sel:BYTE_2
|
||||
|
||||
// NOSICI: error:
|
||||
// NOVI: error:
|
||||
// GFX9: v_cmp_eq_f32_sdwa ttmp[12:13], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0xf8,0x05,0x02]
|
||||
v_cmp_eq_f32_sdwa ttmp[12:13], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
|
||||
|
||||
// NOSICI: error:
|
||||
// NOVI: error:
|
||||
// NO: error: not a valid operand
|
||||
v_cmp_eq_f32_sdwa tba, v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
|
||||
|
||||
// NOSICI: error:
|
||||
// NOVI: error:
|
||||
// NO: error: not a valid operand
|
||||
v_cmp_eq_f32_sdwa tma, v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
|
||||
|
||||
// NOSICI: error:
|
||||
// NOVI: error:
|
||||
// GFX9: v_cmp_eq_f32_sdwa vcc, v1, ttmp15 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0xf6,0x84,0x7c,0x01,0x00,0x05,0x82]
|
||||
v_cmp_eq_f32_sdwa vcc, v1, ttmp15 src0_sel:WORD_1 src1_sel:BYTE_2
|
||||
|
||||
// NOSICI: error:
|
||||
// NOVI: error:
|
||||
// NOGFX9: error: invalid operand (violates constant bus restrictions)
|
||||
|
|
|
|||
|
|
@ -450,6 +450,9 @@
|
|||
# GFX9: v_mov_b32_sdwa v1, s2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x02,0x10,0x86,0x06]
|
||||
0xf9 0x02 0x02 0x7e 0x02 0x10 0x86 0x06
|
||||
|
||||
# GFX9: v_mov_b32_sdwa v1, ttmp12 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x78,0x10,0x86,0x06]
|
||||
0xf9,0x02,0x02,0x7e,0x78,0x10,0x86,0x06
|
||||
|
||||
# GFX9: v_mov_b32_sdwa v1, exec_lo dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x7e,0x10,0x86,0x06]
|
||||
0xf9 0x02 0x02 0x7e 0x7e 0x10 0x86 0x06
|
||||
|
||||
|
|
@ -465,6 +468,9 @@
|
|||
# GFX9: v_cmp_eq_f32_sdwa vcc, v1, s22 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x2c,0x84,0x7c,0x01,0x00,0x05,0x82]
|
||||
0xf9 0x2c 0x84 0x7c 0x01 0x00 0x05 0x82
|
||||
|
||||
# GFX9: v_cmp_eq_f32_sdwa vcc, v1, ttmp15 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0xf6,0x84,0x7c,0x01,0x00,0x05,0x82]
|
||||
0xf9,0xf6,0x84,0x7c,0x01,0x00,0x05,0x82
|
||||
|
||||
#===------------------------------------------------------------------------===#
|
||||
# VOPC with arbitrary SGPR destination
|
||||
#===------------------------------------------------------------------------===#
|
||||
|
|
@ -472,6 +478,9 @@
|
|||
# GFX9: v_cmp_eq_f32_sdwa s[2:3], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0x82,0x05,0x02]
|
||||
0xf9 0x04 0x84 0x7c 0x01 0x82 0x05 0x02
|
||||
|
||||
# GFX9: v_cmp_eq_f32_sdwa ttmp[12:13], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0xf8,0x05,0x02]
|
||||
0xf9,0x04,0x84,0x7c,0x01,0xf8,0x05,0x02
|
||||
|
||||
# GFX9: v_cmp_eq_f32_sdwa exec, v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0xfe,0x05,0x02]
|
||||
0xf9 0x04 0x84 0x7c 0x01 0xfe 0x05 0x02
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,109 @@
|
|||
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
|
||||
|
||||
#===----------------------------------------------------------------------===#
|
||||
# Trap Handler related - 32 bit registers
|
||||
#===----------------------------------------------------------------------===#
|
||||
|
||||
# GFX9: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x6c,0x84,0x6c,0x80]
|
||||
0x6c,0x84,0x6c,0x80
|
||||
|
||||
# GFX9: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x70,0x70,0x80]
|
||||
0x88,0x70,0x70,0x80
|
||||
|
||||
# GFX9: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x70,0xff,0x70,0x80,0x00,0x01,0x00,0x00]
|
||||
0x70,0xff,0x70,0x80,0x00,0x01,0x00,0x00
|
||||
|
||||
# GFX9: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x70,0x84,0x70,0x80]
|
||||
0x70,0x84,0x70,0x80
|
||||
|
||||
# GFX9: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x74,0x70,0x70,0x80]
|
||||
0x74,0x70,0x70,0x80
|
||||
|
||||
# GFX9: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x74,0xff,0x76,0x86,0x80,0x00,0x00,0x00]
|
||||
0x74,0xff,0x76,0x86,0x80,0x00,0x00,0x00
|
||||
|
||||
# GFX9: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x75,0xff,0x75,0x86,0xff,0x01,0x00,0x00]
|
||||
0x75,0xff,0x75,0x86,0xff,0x01,0x00,0x00
|
||||
|
||||
# GFX9: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x75,0x74,0x75,0x86]
|
||||
0x75,0x74,0x75,0x86
|
||||
|
||||
# GFX9: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x6d,0xff,0x74,0x86,0x00,0x00,0x00,0x01]
|
||||
0x6d,0xff,0x74,0x86,0x00,0x00,0x00,0x01
|
||||
|
||||
# GFX9: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x74,0x80,0x00,0xbf]
|
||||
0x74,0x80,0x00,0xbf
|
||||
|
||||
# GFX9: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x74,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
|
||||
0x74,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00
|
||||
|
||||
# GFX9: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x74,0x8c,0x74,0x8f]
|
||||
0x74,0x8c,0x74,0x8f
|
||||
|
||||
# GFX9: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x74,0x02,0x02,0x7e]
|
||||
0x74,0x02,0x02,0x7e
|
||||
|
||||
# GFX9: s_mov_b32 m0, ttmp8 ; encoding: [0x74,0x00,0xfc,0xbe]
|
||||
0x74,0x00,0xfc,0xbe
|
||||
|
||||
# GFX9: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xf6,0xbe]
|
||||
0x80,0x00,0xf6,0xbe
|
||||
|
||||
# GFX9: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xf7,0xbe,0xac,0x4f,0x02,0x01]
|
||||
0xff,0x00,0xf7,0xbe,0xac,0x4f,0x02,0x01
|
||||
|
||||
# GFX9: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x00,0xf4,0xbe]
|
||||
0x7c,0x00,0xf4,0xbe
|
||||
|
||||
# GFX9: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x74,0x74,0x92,0x24,0x03,0x00,0x00]
|
||||
0xff,0x74,0x74,0x92,0x24,0x03,0x00,0x00
|
||||
|
||||
# GFX9: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x75,0xff,0x75,0x87,0x00,0x00,0x28,0x00]
|
||||
0x75,0xff,0x75,0x87,0x00,0x00,0x28,0x00
|
||||
|
||||
# GFX9: s_add_u32 ttmp0, ttmp12, 4 ; encoding: [0x78,0x84,0x6c,0x80]
|
||||
0x78,0x84,0x6c,0x80
|
||||
|
||||
# GFX9: s_add_u32 ttmp0, ttmp13, 4 ; encoding: [0x79,0x84,0x6c,0x80]
|
||||
0x79,0x84,0x6c,0x80
|
||||
|
||||
# GFX9: s_add_u32 ttmp0, ttmp14, 4 ; encoding: [0x7a,0x84,0x6c,0x80]
|
||||
0x7a,0x84,0x6c,0x80
|
||||
|
||||
# GFX9: s_add_u32 ttmp0, ttmp15, 4 ; encoding: [0x7b,0x84,0x6c,0x80]
|
||||
0x7b,0x84,0x6c,0x80
|
||||
|
||||
#===----------------------------------------------------------------------===#
|
||||
# Trap Handler related - Pairs of registers
|
||||
#===----------------------------------------------------------------------===#
|
||||
|
||||
# GFX9: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf0,0xbe]
|
||||
0x7e,0x01,0xf0,0xbe
|
||||
|
||||
# GFX9: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf0,0xbe]
|
||||
0x7e,0x01,0xf0,0xbe
|
||||
|
||||
# GFX9: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x70,0x01,0xfe,0xbe]
|
||||
0x70,0x01,0xfe,0xbe
|
||||
|
||||
# GFX9: s_mov_b64 ttmp[12:13], exec ; encoding: [0x7e,0x01,0xf8,0xbe]
|
||||
0x7e,0x01,0xf8,0xbe
|
||||
|
||||
# GFX9: s_mov_b64 ttmp[14:15], exec ; encoding: [0x7e,0x01,0xfa,0xbe]
|
||||
0x7e,0x01,0xfa,0xbe
|
||||
|
||||
#===----------------------------------------------------------------------===#
|
||||
# Trap Handler related - Some specific instructions and quadruples of registers
|
||||
#===----------------------------------------------------------------------===#
|
||||
|
||||
# GFX9: s_setpc_b64 ttmp[2:3] ; encoding: [0x6e,0x1d,0x80,0xbe]
|
||||
0x6e,0x1d,0x80,0xbe
|
||||
|
||||
# GFX9: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xe8,0x7e]
|
||||
0x01,0x05,0xe8,0x7e
|
||||
|
||||
# GFX9: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1d,0xb8]
|
||||
0x00,0x40,0x2c,0xe1,0x00,0x01,0x1d,0xb8
|
||||
|
||||
# GFX9: buffer_atomic_inc v1, off, ttmp[12:15], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
|
||||
0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8
|
||||
Loading…
Reference in New Issue