VFP/NEON load/store multiple instructions are addrmode4, not 5.
llvm-svn: 113322
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2b88c115f9
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@ -1332,9 +1332,9 @@ class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
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}
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}
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// Load / store multiple
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// Load / store multiple
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class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
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class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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string asm, string cstr, list<dag> pattern>
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: VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
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: VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
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VFPLdStMulFrm, itin, asm, cstr, pattern> {
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VFPLdStMulFrm, itin, asm, cstr, pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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// TODO: Mark the instructions with the appropriate subtarget info.
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let Inst{27-25} = 0b110;
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let Inst{27-25} = 0b110;
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@ -1344,9 +1344,9 @@ class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
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let D = VFPNeonDomain;
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let D = VFPNeonDomain;
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}
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}
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class AXSI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
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class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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string asm, string cstr, list<dag> pattern>
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: VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
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: VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
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VFPLdStMulFrm, itin, asm, cstr, pattern> {
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VFPLdStMulFrm, itin, asm, cstr, pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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// TODO: Mark the instructions with the appropriate subtarget info.
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let Inst{27-25} = 0b110;
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let Inst{27-25} = 0b110;
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@ -133,7 +133,7 @@ def nModImm : Operand<i32> {
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// This is equivalent to VLDMD except that it has a Q register operand
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// This is equivalent to VLDMD except that it has a Q register operand
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// instead of a pair of D registers.
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// instead of a pair of D registers.
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def VLDMQ
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def VLDMQ
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: AXDI5<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p),
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: AXDI4<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p),
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IndexModeNone, IIC_fpLoadm,
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IndexModeNone, IIC_fpLoadm,
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"vldm${addr:submode}${p}\t$addr, ${dst:dregpair}", "",
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"vldm${addr:submode}${p}\t$addr, ${dst:dregpair}", "",
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[(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>;
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[(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>;
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@ -151,7 +151,7 @@ def VLD1q
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// This is equivalent to VSTMD except that it has a Q register operand
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// This is equivalent to VSTMD except that it has a Q register operand
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// instead of a pair of D registers.
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// instead of a pair of D registers.
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def VSTMQ
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def VSTMQ
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: AXDI5<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p),
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: AXDI4<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p),
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IndexModeNone, IIC_fpStorem,
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IndexModeNone, IIC_fpStorem,
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"vstm${addr:submode}${p}\t$addr, ${src:dregpair}", "",
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"vstm${addr:submode}${p}\t$addr, ${src:dregpair}", "",
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[(store (v2f64 QPR:$src), addrmode4:$addr)]>;
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[(store (v2f64 QPR:$src), addrmode4:$addr)]>;
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@ -77,19 +77,19 @@ def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
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//
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//
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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def VLDMD : AXDI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
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def VLDMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
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variable_ops), IndexModeNone, IIC_fpLoadm,
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variable_ops), IndexModeNone, IIC_fpLoadm,
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"vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
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"vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
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let Inst{20} = 1;
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let Inst{20} = 1;
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}
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}
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def VLDMS : AXSI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
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def VLDMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
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variable_ops), IndexModeNone, IIC_fpLoadm,
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variable_ops), IndexModeNone, IIC_fpLoadm,
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"vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
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"vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
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let Inst{20} = 1;
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let Inst{20} = 1;
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}
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}
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def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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reglist:$dsts, variable_ops),
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reglist:$dsts, variable_ops),
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IndexModeUpd, IIC_fpLoadm,
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IndexModeUpd, IIC_fpLoadm,
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"vldm${addr:submode}${p}\t$addr!, $dsts",
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"vldm${addr:submode}${p}\t$addr!, $dsts",
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@ -97,7 +97,7 @@ def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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let Inst{20} = 1;
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let Inst{20} = 1;
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}
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}
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def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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reglist:$dsts, variable_ops),
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reglist:$dsts, variable_ops),
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IndexModeUpd, IIC_fpLoadm,
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IndexModeUpd, IIC_fpLoadm,
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"vldm${addr:submode}${p}\t$addr!, $dsts",
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"vldm${addr:submode}${p}\t$addr!, $dsts",
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@ -107,19 +107,19 @@ def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
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} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
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def VSTMD : AXDI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
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def VSTMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
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variable_ops), IndexModeNone, IIC_fpStorem,
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variable_ops), IndexModeNone, IIC_fpStorem,
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"vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
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"vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
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let Inst{20} = 0;
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let Inst{20} = 0;
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}
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}
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def VSTMS : AXSI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
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def VSTMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
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variable_ops), IndexModeNone, IIC_fpStorem,
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variable_ops), IndexModeNone, IIC_fpStorem,
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"vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
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"vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
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let Inst{20} = 0;
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let Inst{20} = 0;
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}
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}
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def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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reglist:$srcs, variable_ops),
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reglist:$srcs, variable_ops),
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IndexModeUpd, IIC_fpStorem,
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IndexModeUpd, IIC_fpStorem,
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"vstm${addr:submode}${p}\t$addr!, $srcs",
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"vstm${addr:submode}${p}\t$addr!, $srcs",
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@ -127,7 +127,7 @@ def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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let Inst{20} = 0;
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let Inst{20} = 0;
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}
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}
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def VSTMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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reglist:$srcs, variable_ops),
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reglist:$srcs, variable_ops),
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IndexModeUpd, IIC_fpStorem,
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IndexModeUpd, IIC_fpStorem,
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"vstm${addr:submode}${p}\t$addr!, $srcs",
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"vstm${addr:submode}${p}\t$addr!, $srcs",
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