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[WebAssembly] v4f32.abs and v2f64.abs 

Summary: implement lowering of @llvm.fabs for vector types.

Reviewers: aheejin, dschuff

Subscribers:

llvm-svn: 342513
This commit is contained in:
Thomas Lively 2018-09-18 21:45:12 +00:00
parent 258e4f6e4c
commit aaf4e2cbba
3 changed files with 39 additions and 0 deletions
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8
llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
View File

@ -207,6 +207,11 @@ multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond,
!add(baseInst, 1)>;
}
multiclass SIMDAbs<ValueType vec_t, string vec, bits<32> simdop> {
defm ABS_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
[(set (vec_t V128:$dst), (vec_t (fabs V128:$vec)))],
vec#".abs\t$dst, $vec", vec#".abs", simdop>;
}
let Defs = [ARGUMENTS] in {
defm "" : ConstVec<v16i8,
@ -363,6 +368,9 @@ defm GE_S : SIMDConditionInt<"ge_s", SETGE, 106, 2>;
defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 107, 2>;
defm GE : SIMDConditionFP<"ge", SETOGE, 112>;
defm "" : SIMDAbs<v4f32, "f32x4", 116>;
defm "" : SIMDAbs<v2f64, "f64x2", 117>;
} // Defs = [ARGUMENTS]
// Def load and store patterns from WebAssemblyInstrMemory.td for vector types

25
llvm/test/CodeGen/WebAssembly/simd-arith.ll
View File

@ -667,6 +667,18 @@ define <4 x float> @neg_v4f32(<4 x float> %x) {
ret <4 x float> %a
}
; CHECK-LABEL: abs_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: f32x4.abs $push0=, $0{{$}}
; SIMD128-NEXT: return $pop0{{$}}
declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone
define <4 x float> @abs_v4f32(<4 x float> %x) {
%a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
ret <4 x float> %a
}
; CHECK-LABEL: add_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@ -725,6 +737,19 @@ define <2 x double> @neg_v2f64(<2 x double> %x) {
ret <2 x double> %a
}
; CHECK-LABEL: abs_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-NEXT: .param v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: f64x2.abs $push0=, $0{{$}}
; SIMD128-NEXT: return $pop0{{$}}
declare <2 x double> @llvm.fabs.v2f64(<2 x double>) nounwind readnone
define <2 x double> @abs_v2f64(<2 x double> %x) {
%a = call <2 x double> @llvm.fabs.v2f64(<2 x double> %x)
ret <2 x double> %a
}
; CHECK-LABEL: add_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f62x2

6
llvm/test/MC/WebAssembly/simd-encodings.s
View File

@ -325,6 +325,12 @@
# CHECK: f64x2.neg # encoding: [0xfd,0x73]
f64x2.neg
# CHECK: f32x4.abs # encoding: [0xfd,0x74]
f32x4.abs
# CHECK: f64x2.abs # encoding: [0xfd,0x75]
f64x2.abs
# CHECK: f32x4.add # encoding: [0xfd,0x7a]
f32x4.add