Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that.

rdar://problem/9184053

llvm-svn: 128285

llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp

@@ -2951,6 +2951,11 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
   case ARM::WFI:
   case ARM::SEV:
     return true;
+  case ARM::SWP:
+  case ARM::SWPB:
+    // SWP, SWPB: Rd Rm Rn
+    // Delegate to DisassembleLdStExFrm()....
+    return DisassembleLdStExFrm(MI, Opcode, insn, NumOps, NumOpsAdded, B);
   default:
     break;
   }

llvm/test/MC/Disassembler/ARM/arm-tests.txt

@@ -184,3 +184,6 @@
 
 # CHECK:	ldmdb	sp, {r0, r4, r8, r11, r12, pc}
 0x11 0x99 0x1d 0xe9
+
+# CHECK:	swpge	r3, r2, [r6]
+0x92 0x30 0x06 0xa1