- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
- Consolidate instruction formats. - Other clean up. llvm-svn: 58808
This commit is contained in:
Evan Cheng
parent
972fd1a1e0
commit
aa03cd3336
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@ -248,7 +248,7 @@ void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
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}
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void ARMCodeEmitter::emitWordLE(unsigned Binary) {
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DOUT << "\t" << (void*)Binary << "\n";
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DOUT << " " << (void*)Binary << "\n";
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MCE.emitWordLE(Binary);
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}
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@ -282,10 +282,10 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
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case ARMII::MulFrm:
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emitMulFrmInstruction(MI);
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break;
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case ARMII::Branch:
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case ARMII::BrFrm:
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emitBranchInstruction(MI);
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break;
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case ARMII::BranchMisc:
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case ARMII::BrMiscFrm:
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emitMiscBranchInstruction(MI);
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break;
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}
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@ -305,7 +305,7 @@ void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
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ARMConstantPoolValue *ACPV =
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static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
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DOUT << "\t** ARM constant pool #" << CPI << " @ "
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DOUT << " ** ARM constant pool #" << CPI << " @ "
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<< (void*)MCE.getCurrentPCValue() << " " << *ACPV << "\n";
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GlobalValue *GV = ACPV->getGV();
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@ -322,7 +322,7 @@ void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
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} else {
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Constant *CV = MCPE.Val.ConstVal;
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DOUT << "\t** Constant pool #" << CPI << " @ "
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DOUT << " ** Constant pool #" << CPI << " @ "
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<< (void*)MCE.getCurrentPCValue() << " " << *CV << "\n";
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if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
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@ -380,7 +380,7 @@ void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
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}
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void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
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DOUT << "\t** LPC" << LabelID << " @ "
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DOUT << " ** LPC" << LabelID << " @ "
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<< (void*)MCE.getCurrentPCValue() << '\n';
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JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
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}
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@ -566,8 +566,6 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
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void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
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unsigned ImplicitRn) {
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const TargetInstrDesc &TID = MI.getDesc();
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// Part of binary is determined by TableGn.
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unsigned Binary = getBinaryCodeForInstr(MI);
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@ -621,8 +619,6 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
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void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
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unsigned ImplicitRn) {
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const TargetInstrDesc &TID = MI.getDesc();
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// Part of binary is determined by TableGn.
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unsigned Binary = getBinaryCodeForInstr(MI);
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@ -751,6 +747,9 @@ void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
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void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
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const TargetInstrDesc &TID = MI.getDesc();
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if (TID.Opcode == ARM::TPsoft)
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abort(); // FIXME
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// Part of binary is determined by TableGn.
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unsigned Binary = getBinaryCodeForInstr(MI);
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@ -771,7 +770,10 @@ void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
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void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
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const TargetInstrDesc &TID = MI.getDesc();
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if (TID.Opcode == ARM::BX)
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if (TID.Opcode == ARM::BX ||
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TID.Opcode == ARM::BR_JTr ||
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TID.Opcode == ARM::BR_JTm ||
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TID.Opcode == ARM::BR_JTadd)
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abort(); // FIXME
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// Part of binary is determined by TableGn.
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@ -21,8 +21,8 @@ class Format<bits<5> val> {
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def Pseudo : Format<1>;
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def MulFrm : Format<2>;
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def Branch : Format<3>;
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def BranchMisc : Format<4>;
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def BrFrm : Format<3>;
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def BrMiscFrm : Format<4>;
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def DPFrm : Format<5>;
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def DPSoRegFrm : Format<6>;
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@ -134,40 +134,25 @@ class AXI<dag oops, dag iops, Format f, string asm,
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"", pattern>;
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// Ctrl flow instructions
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class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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class ABI<bits<4> opcod, dag oops, dag iops, string opc,
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string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, opc,
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asm,"",pattern> {
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let Inst{27-24} = opcod;
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}
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class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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: XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
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class ABXI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
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: XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, asm,
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"", pattern> {
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let Inst{27-24} = opcod;
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}
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// FIXME: BX
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class AXIx2<dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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: XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
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class ABXIx2<dag oops, dag iops, string asm, list<dag> pattern>
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: XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, asm,
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"", pattern>;
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class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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: XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
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"", pattern> {
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let Inst{27-24} = opcod;
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}
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class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
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asm,"",pattern> {
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let Inst{27-24} = opcod;
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}
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// BR_JT instructions
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// == mov pc
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class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
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: XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
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: XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm,
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asm, "", pattern> {
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let Inst{20} = 0; // S Bit
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let Inst{24-21} = opcod;
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@ -175,7 +160,7 @@ class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
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}
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// == add pc
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class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
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: XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
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: XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BrMiscFrm,
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asm, "", pattern> {
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let Inst{20} = 0; // S bit
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let Inst{24-21} = opcod;
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@ -183,7 +168,7 @@ class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
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}
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// == ldr pc
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class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
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: XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
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: XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BrMiscFrm,
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asm, "", pattern> {
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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@ -641,29 +626,14 @@ class AI3sthpo<dag oops, dag iops, Format f, string opc,
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// addrmode4 instructions
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class AI4<dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern> {
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let Inst{25-27} = {0,0,1};
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}
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class AXI4ld<dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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class AXI4ld<dag oops, dag iops, Format f, string asm, list<dag> pattern>
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: XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
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"", pattern> {
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let Inst{20} = 1; // L bit
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let Inst{22} = 0; // S bit
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let Inst{27-25} = 0b100;
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}
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class AXI4ldpc<dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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: XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
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"", pattern> {
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let Inst{20} = 1; // L bit
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let Inst{27-25} = 0b100;
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}
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class AXI4st<dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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class AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern>
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: XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
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"", pattern> {
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let Inst{20} = 0; // L bit
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@ -79,8 +79,8 @@ namespace ARMII {
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MulFrm = 2 << FormShift,
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// Branch instructions
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Branch = 3 << FormShift,
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BranchMisc = 4 << FormShift,
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BrFrm = 3 << FormShift,
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BrMiscFrm = 4 << FormShift,
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// Data Processing instructions
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DPFrm = 5 << FormShift,
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@ -465,6 +465,8 @@ PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
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".loc $file, $line, $col",
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[(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
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// Address computation and loads and stores in PIC mode.
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let isNotDuplicable = 1 in {
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def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
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Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
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@ -505,14 +507,14 @@ def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
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Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
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[(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
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}
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}
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} // isNotDuplicable = 1
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions.
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//
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let isReturn = 1, isTerminator = 1 in
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def BX_RET : AI<(outs), (ins), BranchMisc, "bx", " lr", [(ARMretflag)]> {
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def BX_RET : AI<(outs), (ins), BrMiscFrm, "bx", " lr", [(ARMretflag)]> {
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let Inst{7-4} = 0b0001;
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let Inst{19-8} = 0b111111111111;
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let Inst{27-20} = 0b00010010;
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@ -521,8 +523,9 @@ let isReturn = 1, isTerminator = 1 in
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// FIXME: remove when we have a way to marking a MI with these properties.
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// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
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// operand list.
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// FIXME: Should pc be an implicit operand like PICADD, etc?
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let isReturn = 1, isTerminator = 1 in
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def LDM_RET : AXI4ldpc<(outs),
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def LDM_RET : AXI4ld<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
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LdMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
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[]>;
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@ -530,16 +533,16 @@ let isReturn = 1, isTerminator = 1 in
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let isCall = 1,
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Defs = [R0, R1, R2, R3, R12, LR,
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D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
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def BL : ABLI<0b1011, (outs), (ins i32imm:$func, variable_ops), Branch,
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def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
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"bl ${func:call}",
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[(ARMcall tglobaladdr:$func)]>;
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def BL_pred : ABLpredI<0b1011, (outs), (ins i32imm:$func, variable_ops), Branch,
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def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
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"bl", " ${func:call}",
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[(ARMcall_pred tglobaladdr:$func)]>;
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// ARMv5T and above
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def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BranchMisc,
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def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
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"blx $func",
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[(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]> {
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let Inst{7-4} = 0b0011;
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@ -549,8 +552,8 @@ let isCall = 1,
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let Uses = [LR] in {
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// ARMv4T
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def BX : AXIx2<(outs), (ins GPR:$func, variable_ops),
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BranchMisc, "mov lr, pc\n\tbx $func",
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def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
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"mov lr, pc\n\tbx $func",
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[(ARMcall_nolink GPR:$func)]>;
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}
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}
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@ -559,7 +562,7 @@ let isBranch = 1, isTerminator = 1 in {
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// B is "predicable" since it can be xformed into a Bcc.
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let isBarrier = 1 in {
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let isPredicable = 1 in
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def B : ABI<0b1010, (outs), (ins brtarget:$target), Branch, "b $target",
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def B : ABXI<0b1010, (outs), (ins brtarget:$target), "b $target",
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[(br bb:$target)]>;
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let isNotDuplicable = 1, isIndirectBranch = 1 in {
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@ -583,7 +586,7 @@ let isBranch = 1, isTerminator = 1 in {
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// FIXME: should be able to write a pattern for ARMBrcond, but can't use
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// a two-value operand where a dag node expects two operands. :(
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def Bcc : ABccI<0b1010, (outs), (ins brtarget:$target), Branch,
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def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
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"b", " $target",
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[/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
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}
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@ -963,7 +966,6 @@ def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
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let Inst{7-4} = 0b1101;
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}
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// FIXME: encoding
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multiclass AI_smul<string opc, PatFrag opnode> {
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def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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!strconcat(opc, "bb"), " $dst, $a, $b",
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@ -1021,7 +1023,6 @@ multiclass AI_smul<string opc, PatFrag opnode> {
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}
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// FIXME: encoding
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multiclass AI_smla<string opc, PatFrag opnode> {
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def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
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!strconcat(opc, "bb"), " $dst, $a, $b, $acc",
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@ -1142,7 +1143,6 @@ def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
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(and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
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(PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
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//===----------------------------------------------------------------------===//
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// Comparison Instructions...
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//
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@ -1215,7 +1215,7 @@ def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred
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// __aeabi_read_tp preserves the registers r1-r3.
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let isCall = 1,
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Defs = [R0, R12, LR, CPSR] in {
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def TPsoft : AXI<(outs), (ins), BranchMisc,
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def TPsoft : ABXI<0b1011, (outs), (ins),
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"bl __aeabi_read_tp",
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[(set R0, ARMthread_pointer)]>;
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}
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