ELF: Perform per-section .ARM.exidx processing during combineEhFrameSections(). NFCI.
And rename the function to combineEhSections(). This makes the processing of .ARM.exidx even more similar to .eh_frame and means that we can avoid an additional loop over InputSections. Differential Revision: https://reviews.llvm.org/D60026 llvm-svn: 357417
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@ -3041,37 +3041,7 @@ MipsRldMapSection::MipsRldMapSection()
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ARMExidxSyntheticSection::ARMExidxSyntheticSection()
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: SyntheticSection(SHF_ALLOC | SHF_LINK_ORDER, SHT_ARM_EXIDX,
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Config->Wordsize, ".ARM.exidx") {
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for (InputSectionBase *&IS : InputSections) {
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if (isa<InputSection>(IS) && IS->Type == SHT_ARM_EXIDX) {
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ExidxSections.push_back(cast<InputSection>(IS));
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IS = nullptr;
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} else if (IS->Live && isa<InputSection>(IS) &&
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IS->kind() != SectionBase::Synthetic &&
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(IS->Flags & SHF_ALLOC) && (IS->Flags & SHF_EXECINSTR) &&
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IS->getSize() > 0) {
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ExecutableSections.push_back(cast<InputSection>(IS));
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}
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}
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setSizeAndOffsets();
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// FIXME: we do not output a relocation section when --emit-relocs is used
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// as we do not have relocation sections for linker generated table entries
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// and we would have to erase at a late stage relocations from merged entries.
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// Given that exception tables are already position independent and a binary
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// analyzer could derive the relocations we choose to erase the relocations.
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if (Config->EmitRelocs)
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for (InputSectionBase *&IS : InputSections)
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if (IS && isa<InputSection>(IS) && IS->Type == SHT_REL) {
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InputSection *RS = cast<InputSection>(IS);
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if (InputSectionBase *EX = RS->getRelocatedSection())
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if (isa<InputSection>(EX) && EX->Type == SHT_ARM_EXIDX)
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IS = nullptr;
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}
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std::vector<InputSectionBase *> &V = InputSections;
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V.erase(std::remove(V.begin(), V.end(), nullptr), V.end());
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}
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Config->Wordsize, ".ARM.exidx") {}
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static InputSection *findExidxSection(InputSection *IS) {
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for (InputSection *D : IS->DependentSections)
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@ -3080,21 +3050,31 @@ static InputSection *findExidxSection(InputSection *IS) {
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return nullptr;
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}
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void ARMExidxSyntheticSection::setSizeAndOffsets() {
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size_t Offset = 0;
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Size = 0;
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for (InputSection *IS : ExecutableSections) {
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if (InputSection *D = findExidxSection(IS)) {
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D->OutSecOff = Offset;
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D->Parent = getParent();
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Offset += D->getSize();
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Empty = false;
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} else {
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Offset += 8;
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}
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bool ARMExidxSyntheticSection::addSection(InputSection *IS) {
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if (IS->Type == SHT_ARM_EXIDX) {
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ExidxSections.push_back(IS);
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return true;
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}
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// Size includes Sentinel.
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Size = Offset + 8;
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if ((IS->Flags & SHF_ALLOC) && (IS->Flags & SHF_EXECINSTR) &&
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IS->getSize() > 0) {
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ExecutableSections.push_back(IS);
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if (Empty && findExidxSection(IS))
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Empty = false;
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return false;
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}
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// FIXME: we do not output a relocation section when --emit-relocs is used
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// as we do not have relocation sections for linker generated table entries
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// and we would have to erase at a late stage relocations from merged entries.
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// Given that exception tables are already position independent and a binary
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// analyzer could derive the relocations we choose to erase the relocations.
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if (Config->EmitRelocs && IS->Type == SHT_REL)
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if (InputSectionBase *EX = IS->getRelocatedSection())
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if (isa<InputSection>(EX) && EX->Type == SHT_ARM_EXIDX)
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return true;
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return false;
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}
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// References to .ARM.Extab Sections have bit 31 clear and are not the
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@ -3181,7 +3161,20 @@ void ARMExidxSyntheticSection::finalizeContents() {
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}
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ExecutableSections = std::move(SelectedSections);
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}
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setSizeAndOffsets();
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size_t Offset = 0;
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Size = 0;
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for (InputSection *IS : ExecutableSections) {
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if (InputSection *D = findExidxSection(IS)) {
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D->OutSecOff = Offset;
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D->Parent = getParent();
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Offset += D->getSize();
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} else {
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Offset += 8;
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}
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}
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// Size includes Sentinel.
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Size = Offset + 8;
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}
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InputSection *ARMExidxSyntheticSection::getLinkOrderDep() const {
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@ -975,6 +975,11 @@ public:
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class ARMExidxSyntheticSection : public SyntheticSection {
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public:
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ARMExidxSyntheticSection();
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// Add an input section to the ARMExidxSyntheticSection. Returns whether the
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// section needs to be removed from the main input section list.
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bool addSection(InputSection *IS);
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size_t getSize() const override { return Size; }
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void writeTo(uint8_t *Buf) override;
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bool isNeeded() const override { return !Empty; }
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@ -989,9 +994,6 @@ public:
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std::vector<InputSection *> ExidxSections;
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private:
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// Derive Size from contents of ExecutableSections, including any linker
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// generated sentinels. Also set the OutSecOff of the ExidxSections.
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void setSizeAndOffsets();
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size_t Size;
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// Empty if ExecutableSections contains no dependent .ARM.exidx sections.
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@ -152,14 +152,18 @@ template <class ELFT> void Writer<ELFT>::removeEmptyPTLoad() {
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});
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}
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template <class ELFT> static void combineEhFrameSections() {
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template <class ELFT> static void combineEhSections() {
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for (InputSectionBase *&S : InputSections) {
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EhInputSection *ES = dyn_cast<EhInputSection>(S);
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if (!ES || !ES->Live)
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if (!S->Live)
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continue;
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In.EhFrame->addSection<ELFT>(ES);
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S = nullptr;
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if (auto *ES = dyn_cast<EhInputSection>(S)) {
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In.EhFrame->addSection<ELFT>(ES);
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S = nullptr;
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} else if (S->kind() == SectionBase::Regular && In.ARMExidx &&
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In.ARMExidx->addSection(cast<InputSection>(S))) {
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S = nullptr;
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}
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}
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std::vector<InputSectionBase *> &V = InputSections;
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@ -465,8 +469,11 @@ template <class ELFT> void Writer<ELFT>::run() {
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// Such sections are of type input section.
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createSyntheticSections<ELFT>();
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// Some input sections that are used for exception handling need to be moved
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// into synthetic sections. Do that now so that they aren't assigned to
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// output sections in the usual way.
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if (!Config->Relocatable)
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combineEhFrameSections<ELFT>();
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combineEhSections<ELFT>();
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// We want to process linker script commands. When SECTIONS command
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// is given we let it create sections.
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