[Sparc] Rearrange SparcInstrInfo, no change.
Move some instructions into order of sections in the spec, as the rest already were. Differential Revision: http://reviews.llvm.org/D9102 llvm-svn: 241163
This commit is contained in:
James Y Knight
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33d99d6077
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a8a8c605ee
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@ -353,13 +353,6 @@ let hasSideEffects = 1, mayStore = 1 in {
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[(flushw)]>;
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}
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let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
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def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
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let rd = 0 in
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def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
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"unimp $imm22", []>;
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
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// instruction selection into a branch sequence. This has to handle all
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// permutations of selection between i32/f32/f64 on ICC and FCC.
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@ -406,36 +399,6 @@ let usesCustomInserter = 1, Uses = [FCC0] in {
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[(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
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}
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// JMPL Instruction.
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let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
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DecoderMethod = "DecodeJMPL" in {
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def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
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"jmpl $addr, $dst", []>;
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def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
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"jmpl $addr, $dst", []>;
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}
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// Section A.3 - Synthetic Instructions, p. 85
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// special cases of JMPL:
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let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
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isCodeGenOnly = 1 in {
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let rd = 0, rs1 = 15 in
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def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
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"jmp %o7+$val", [(retflag simm13:$val)]>;
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let rd = 0, rs1 = 31 in
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def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
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"jmp %i7+$val", []>;
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}
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let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
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isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
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def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr),
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"rett $addr", []>;
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def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr),
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"rett $addr", []>;
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}
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// Section B.1 - Load Integer Instructions, p. 90
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let DecoderMethod = "DecodeLoadInt" in {
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defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>;
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@ -470,6 +433,24 @@ let DecoderMethod = "DecodeStoreQFP" in
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defm STQF : Store<"stq", 0b100110, store, QFPRegs, f128>,
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Requires<[HasV9, HasHardQuad]>;
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// Section B.8 - SWAP Register with Memory Instruction
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// (Atomic swap)
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let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
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def SWAPrr : F3_1<3, 0b001111,
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(outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
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"swap [$addr], $dst",
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[(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
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def SWAPri : F3_2<3, 0b001111,
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(outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
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"swap [$addr], $dst",
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[(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
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def SWAPArr : F3_1_asi<3, 0b011111,
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(outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
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"swapa [$addr] $asi, $dst",
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[/*FIXME: pattern?*/]>;
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}
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// Section B.9 - SETHI Instruction, p. 104
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def SETHIi: F2_1<0b100,
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(outs IntRegs:$rd), (ins i32imm:$imm22),
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@ -725,6 +706,56 @@ let Uses = [O6],
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}
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}
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// Section B.25 - Jump and Link Instruction
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// JMPL Instruction.
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let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
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DecoderMethod = "DecodeJMPL" in {
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def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
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"jmpl $addr, $dst", []>;
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def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
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"jmpl $addr, $dst", []>;
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}
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// Section A.3 - Synthetic Instructions, p. 85
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// special cases of JMPL:
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let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
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isCodeGenOnly = 1 in {
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let rd = 0, rs1 = 15 in
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def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
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"jmp %o7+$val", [(retflag simm13:$val)]>;
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let rd = 0, rs1 = 31 in
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def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
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"jmp %i7+$val", []>;
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}
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// Section B.26 - Return from Trap Instruction
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let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
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isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
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def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr),
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"rett $addr", []>;
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def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr),
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"rett $addr", []>;
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}
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// Section B.27 - Trap on Integer Condition Codes Instruction
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multiclass TRAP<string regStr> {
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def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2,
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CCOp:$cond),
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!strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), []>;
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def ri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm,
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CCOp:$cond),
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!strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), []>;
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}
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let hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
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defm TICC : TRAP<"%icc">;
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let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
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def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
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// Section B.28 - Read State Register Instructions
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let rs2 = 0 in
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def RDASR : F3_1<2, 0b101000,
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@ -787,6 +818,18 @@ let Predicates = [HasNoV9] in {
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}
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}
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// Section B.30 - STBAR Instruction
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let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in
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def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
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// Section B.31 - Unimplmented Instruction
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let rd = 0 in
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def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
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"unimp $imm22", []>;
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// Section B.33 - Floating-point Operate (FPop) Instructions
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// Convert Integer to Floating-point Instructions, p. 141
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def FITOS : F3_3u<2, 0b110100, 0b011000100,
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(outs FPRegs:$rd), (ins FPRegs:$rs2),
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@ -1168,29 +1211,10 @@ let rs1 = 0 in
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def : Pat<(ctpop i32:$src),
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(POPCrr (SRLri $src, 0))>;
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// Atomic swap.
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let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0 in
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def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
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let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
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def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
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"membar $simm13", []>;
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let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
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def SWAPrr : F3_1<3, 0b001111,
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(outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
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"swap [$addr], $dst",
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[(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
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def SWAPri : F3_2<3, 0b001111,
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(outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
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"swap [$addr], $dst",
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[(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
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def SWAPArr : F3_1_asi<3, 0b011111,
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(outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
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"swapa [$addr] $asi, $dst",
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[/*FIXME: pattern?*/]>;
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}
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// TODO: Should add a CASArr variant. In fact, the CAS instruction,
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// unlike other instructions, only comes in a form which requires an
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// ASI be provided. The ASI value hardcoded here is ASI_PRIMARY, the
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@ -1215,18 +1239,6 @@ let hasSideEffects = 1 in {
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}
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}
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multiclass TRAP<string regStr> {
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def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2,
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CCOp:$cond),
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!strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), []>;
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def ri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm,
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CCOp:$cond),
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!strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), []>;
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}
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let hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
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defm TICC : TRAP<"%icc">;
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//===----------------------------------------------------------------------===//
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