[AArch64][x86] add tests for bitcasted fnabs; NFC
Alternate target coverage for D44548. llvm-svn: 344059
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@ -34,5 +34,55 @@ define float @still_not_fabs(float %x) #0 {
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ret float %cond
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}
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define float @nabsf(float %a) {
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; CHECK-LABEL: nabsf:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: orr w8, w8, #0x80000000
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: ret
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%conv = bitcast float %a to i32
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%and = or i32 %conv, -2147483648
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%conv1 = bitcast i32 %and to float
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ret float %conv1
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}
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define double @nabsd(double %a) {
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; CHECK-LABEL: nabsd:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov x8, d0
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; CHECK-NEXT: orr x8, x8, #0x8000000000000000
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; CHECK-NEXT: fmov d0, x8
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; CHECK-NEXT: ret
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%conv = bitcast double %a to i64
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%and = or i64 %conv, -9223372036854775808
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%conv1 = bitcast i64 %and to double
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ret double %conv1
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}
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define <4 x float> @nabsv4f32(<4 x float> %a) {
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; CHECK-LABEL: nabsv4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr v0.4s, #128, lsl #24
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; CHECK-NEXT: ret
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%conv = bitcast <4 x float> %a to <4 x i32>
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%and = or <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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%conv1 = bitcast <4 x i32> %and to <4 x float>
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ret <4 x float> %conv1
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}
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define <2 x double> @nabsv2d64(<2 x double> %a) {
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; CHECK-LABEL: nabsv2d64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr x8, xzr, #0x8000000000000000
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; CHECK-NEXT: dup v1.2d, x8
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; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%conv = bitcast <2 x double> %a to <2 x i64>
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%and = or <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808>
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%conv1 = bitcast <2 x i64> %and to <2 x double>
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ret <2 x double> %conv1
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}
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attributes #0 = { "no-nans-fp-math"="true" }
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@ -308,6 +308,52 @@ define float @fsub_bitcast_fneg(float %x, float %y) {
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ret float %fsub
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}
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define float @nabsf(float %a) {
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; CHECK-LABEL: nabsf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%conv = bitcast float %a to i32
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%and = or i32 %conv, -2147483648
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%conv1 = bitcast i32 %and to float
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ret float %conv1
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}
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define double @nabsd(double %a) {
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; CHECK-LABEL: nabsd:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%conv = bitcast double %a to i64
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%and = or i64 %conv, -9223372036854775808
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%conv1 = bitcast i64 %and to double
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ret double %conv1
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}
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define <4 x float> @nabsv4f32(<4 x float> %a) {
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; CHECK-LABEL: nabsv4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: orps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%conv = bitcast <4 x float> %a to <4 x i32>
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%and = or <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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%conv1 = bitcast <4 x i32> %and to <4 x float>
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ret <4 x float> %conv1
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}
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define <2 x double> @nabsv2d64(<2 x double> %a) {
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; CHECK-LABEL: nabsv2d64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: orps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%conv = bitcast <2 x double> %a to <2 x i64>
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%and = or <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808>
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%conv1 = bitcast <2 x i64> %and to <2 x double>
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ret <2 x double> %conv1
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}
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define <4 x float> @fadd_bitcast_fneg_vec(<4 x float> %x, <4 x float> %y) {
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; CHECK-LABEL: fadd_bitcast_fneg_vec:
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; CHECK: # %bb.0:
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