Revert "bar"
This reverts commit r271365. Sorry, wrong branch. llvm-svn: 271366
This commit is contained in:
Rafael Espindola
parent
74540516ef
commit
a8433c1d1b
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@ -257,8 +257,6 @@ getSymVA(uint32_t Type, typename ELFT::uint A, typename ELFT::uint P,
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case R_PC:
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case R_RELAX_GOT_PC:
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return Body.getVA<ELFT>(A) - P;
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case R_RELAX_GOT_PC_NOPIC:
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return Body.getVA<ELFT>();
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case R_PAGE_PC:
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return getAArch64Page(Body.getVA<ELFT>(A)) - getAArch64Page(P);
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}
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@ -327,7 +325,6 @@ void InputSectionBase<ELFT>::relocate(uint8_t *Buf, uint8_t *BufEnd) {
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switch (Expr) {
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case R_RELAX_GOT_PC:
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case R_RELAX_GOT_PC_NOPIC:
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Target->relaxGot(BufLoc, SymVA);
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break;
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case R_RELAX_TLS_IE_TO_LE:
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@ -244,7 +244,7 @@ static bool needsPlt(RelExpr Expr) {
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// file (PC, or GOT for example).
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static bool isRelExpr(RelExpr Expr) {
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return Expr == R_PC || Expr == R_GOTREL || Expr == R_PAGE_PC ||
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Expr == R_RELAX_GOT_PC || Expr == R_RELAX_GOT_PC_NOPIC;
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Expr == R_RELAX_GOT_PC;
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}
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template <class ELFT>
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@ -370,8 +370,8 @@ static RelExpr adjustExpr(const elf::ObjectFile<ELFT> &File, SymbolBody &Body,
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} else if (!Preemptible) {
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if (needsPlt(Expr))
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Expr = fromPlt(Expr);
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if (Expr == R_GOT_PC)
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Expr = Target->adjustRelaxGotExpr(Type, Data + Offset, Expr);
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if (Expr == R_GOT_PC && Target->canRelaxGot(Type, Data + Offset))
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Expr = R_RELAX_GOT_PC;
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}
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if (IsWrite || isStaticLinkTimeConstant<ELFT>(Expr, Type, Body))
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@ -39,7 +39,6 @@ enum RelExpr {
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R_PPC_PLT_OPD,
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R_PPC_TOC,
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R_RELAX_GOT_PC,
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R_RELAX_GOT_PC_NOPIC,
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R_RELAX_TLS_GD_TO_IE,
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R_RELAX_TLS_GD_TO_LE,
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R_RELAX_TLS_IE_TO_LE,
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@ -113,8 +113,7 @@ public:
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int32_t Index, unsigned RelOff) const override;
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void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
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RelExpr adjustRelaxGotExpr(uint32_t Type, const uint8_t *Data,
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RelExpr Expr) const override;
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bool canRelaxGot(uint32_t Type, const uint8_t *Data) const override;
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void relaxGot(uint8_t *Loc, uint64_t Val) const override;
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void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
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void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
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@ -235,9 +234,8 @@ bool TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const {
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return false;
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}
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RelExpr TargetInfo::adjustRelaxGotExpr(uint32_t Type, const uint8_t *Data,
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RelExpr Expr) const {
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return Expr;
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bool TargetInfo::canRelaxGot(uint32_t Type, const uint8_t *Data) const {
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return false;
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}
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void TargetInfo::relaxGot(uint8_t *Loc, uint64_t Val) const {
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@ -736,25 +734,16 @@ void X86_64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
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}
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}
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RelExpr X86_64TargetInfo::adjustRelaxGotExpr(uint32_t Type, const uint8_t *Data,
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RelExpr RelExpr) const {
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bool X86_64TargetInfo::canRelaxGot(uint32_t Type, const uint8_t *Data) const {
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if (Type != R_X86_64_GOTPCRELX && Type != R_X86_64_REX_GOTPCRELX)
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return RelExpr;
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return false;
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const uint8_t Op = Data[-2];
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const uint8_t ModRm = Data[-1];
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// Relax mov.
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if (Op == 0x8b)
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return R_RELAX_GOT_PC;
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return true;
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// Relax call and jmp.
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if (Op == 0xff && (ModRm == 0x15 || ModRm == 0x25))
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return R_RELAX_GOT_PC;
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// Relaxation of test, adc, add, and, cmp, or, sbb, sub, xor.
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// If PIC then no relaxation is available.
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// We also don't relax test/binop instructions without REX byte,
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// they are 32bit operations and not common to have.
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return (!Config->Pic && Type == R_X86_64_REX_GOTPCRELX) ? R_RELAX_GOT_PC_NOPIC
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: RelExpr;
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return Op == 0xff && (ModRm == 0x15 || ModRm == 0x25);
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}
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void X86_64TargetInfo::relaxGot(uint8_t *Loc, uint64_t Val) const {
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@ -768,86 +757,22 @@ void X86_64TargetInfo::relaxGot(uint8_t *Loc, uint64_t Val) const {
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return;
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}
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// Convert call/jmp instructions.
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if (Op == 0xff) {
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if (ModRm == 0x15) {
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// ABI says we can convert call *foo@GOTPCREL(%rip) to nop call foo.
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// Instead we convert to addr32 call foo, where addr32 is instruction
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// prefix. That makes result expression to be a single instruction.
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*(Loc - 2) = 0x67; // addr32 prefix
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*(Loc - 1) = 0xe8; // call
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}
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else {
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assert(ModRm == 0x25);
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// Convert jmp *foo@GOTPCREL(%rip) to jmp foo nop.
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// jmp doesn't return, so it is fine to use nop here, it is just a stub.
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*(Loc - 2) = 0xe9; // jmp
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*(Loc + 3) = 0x90; // nop
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Loc -= 1;
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Val += 1;
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}
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relocateOne(Loc, R_X86_64_PC32, Val);
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return;
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assert(Op == 0xff);
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if (ModRm == 0x15) {
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// ABI says we can convert call *foo@GOTPCREL(%rip) to nop call foo.
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// Instead we convert to addr32 call foo, where addr32 is instruction
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// prefix. That makes result expression to be a single instruction.
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*(Loc - 2) = 0x67; // addr32 prefix
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*(Loc - 1) = 0xe8; // call
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} else {
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assert(ModRm == 0x25);
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// Convert jmp *foo@GOTPCREL(%rip) to jmp foo nop.
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// jmp doesn't return, so it is fine to use nop here, it is just a stub.
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*(Loc - 2) = 0xe9; // jmp
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*(Loc + 3) = 0x90; // nop
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Loc -= 1;
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Val += 1;
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}
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// Convert "test %reg, foo@GOTPCREL(%rip)" to "test $foo, %reg".
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// Documents used:
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// 1) http://ref.x86asm.net/coder64.html
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// 2) http://wiki.osdev.org/X86-64_Instruction_Encoding
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// 3) http://www.swansontec.com/sintel.html
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assert(!Config->Pic);
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const uint8_t Rex = Loc[-3];
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if (Op == 0x85) {
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// See 0x85 description in (1). Column "o" has "r" what indicates that the
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// instruction uses "full" ModR / M byte, (no opcode extension).
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// ModR/M byte has form XX YYY ZZZ, where
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// YYY is MODRM.reg(register 2), ZZZ is MODRM.rm(register 1).
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// XX has different meanings:
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// 00: The operand's memory address is in reg1.
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// 01: The operand's memory address is reg1 + a byte-sized displacement.
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// 10: The operand's memory address is reg1 + a word-sized displacement.
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// 11: The operand is reg1 itself.
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// If an instruction requires only one operand, the unused reg2 field
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// holds extra opcode bits rather than a register code
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// 0xC0 == 11 000 000 binary.
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// 0x38 == 00 111 000 binary.
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// We transfer reg2 to reg1 here as operand. See (2), (3).
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*(Loc - 1) = 0xc0 | (ModRm & 0x38) >> 3; // ModR/M byte.
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// Change opcode from test op1 = r/m16/32/64, op2 = r16/32/64
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// to test op1 = r/m16/32/64, op2 = imm16/32/64, see (1).
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*(Loc - 2) = 0xf7;
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// Move R bit to the B bit in REX byte.
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// REX byte is encoded as 0100WRXB, where
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// 0100 is 4bit fixed pattern.
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// REX.W When 1, a 64-bit operand size is used. Otherwise, when 0, the
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// default operand size is used (which is 32-bit for most but not all
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// instructions).
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// REX.R This 1-bit value is an extension to the MODRM.reg field.
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// REX.X This 1-bit value is an extension to the SIB.index field.
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// REX.B This 1-bit value is an extension to the MODRM.rm field or the
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// SIB.base field, see (3).
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*(Loc - 3) = (Rex & ~0x4) | (Rex & 0x4) >> 2;
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relocateOne(Loc, R_X86_64_PC32, Val);
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return;
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}
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// If we are here then we need to relax the adc, add, and, cmp, or, sbb, sub
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// or xor operations.
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// Convert "binop foo@GOTPCREL(%rip), %reg" to "binop $foo, %reg".
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// Logic is close to one for test instruction above, but we also
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// write opcode extension here, see below for info.
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*(Loc - 1) = 0xc0 | (ModRm & 0x38) >> 3 | (Op & 0x3c); // ModR/M byte.
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// Primary opcode is 0x81, opcode extension is one of:
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// 000b = ADD, 001b is OR, 010b is ADC, 011b is SBB,
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// 100b is AND, 101b is SUB, 110b is XOR, 111b is CMP.
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// This value was wrote to MODRM.reg in a line above, see (1).
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*(Loc - 2) = 0x81;
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*(Loc - 3) = (Rex & ~0x4) | (Rex & 0x4) >> 2;
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relocateOne(Loc, R_X86_64_PC32, Val);
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}
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@ -88,8 +88,7 @@ public:
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uint32_t ThunkSize = 0;
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virtual RelExpr adjustRelaxGotExpr(uint32_t Type, const uint8_t *Data,
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RelExpr Expr) const;
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virtual bool canRelaxGot(uint32_t Type, const uint8_t *Data) const;
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virtual void relaxGot(uint8_t *Loc, uint64_t Val) const;
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virtual void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const;
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virtual void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const;
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@ -1,109 +0,0 @@
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# REQUIRES: x86
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# RUN: llvm-mc -filetype=obj -relax-relocations -triple=x86_64-unknown-linux %s -o %t.o
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# RUN: ld.lld %t.o -o %t1
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# RUN: llvm-readobj -symbols -r %t1 | FileCheck --check-prefix=SYMRELOC %s
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# RUN: llvm-objdump -d %t1 | FileCheck --check-prefix=DISASM %s
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## There is no relocations.
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# SYMRELOC: Relocations [
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# SYMRELOC-NEXT: ]
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# SYMRELOC: Symbols [
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# SYMRELOC: Symbol {
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# SYMRELOC: Name: bar
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# SYMRELOC-NEXT: Value: 0x13000
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## 77824 = 0x13000 (bar)
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## Notice, that 32bit versions of operations are not relaxed.
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# DISASM: Disassembly of section .text:
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# DISASM-NEXT: _start:
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# DISASM-NEXT: 11000: 13 05 fa 0f 00 00 adcl 4090(%rip), %eax
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# DISASM-NEXT: 11006: 03 1d f4 0f 00 00 addl 4084(%rip), %ebx
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# DISASM-NEXT: 1100c: 23 0d ee 0f 00 00 andl 4078(%rip), %ecx
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# DISASM-NEXT: 11012: 3b 15 e8 0f 00 00 cmpl 4072(%rip), %edx
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# DISASM-NEXT: 11018: 0b 35 e2 0f 00 00 orl 4066(%rip), %esi
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# DISASM-NEXT: 1101e: 1b 3d dc 0f 00 00 sbbl 4060(%rip), %edi
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# DISASM-NEXT: 11024: 2b 2d d6 0f 00 00 subl 4054(%rip), %ebp
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# DISASM-NEXT: 1102a: 44 33 05 cf 0f 00 00 xorl 4047(%rip), %r8d
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# DISASM-NEXT: 11031: 44 85 3d c8 0f 00 00 testl 4040(%rip), %r15d
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# DISASM-NEXT: 11038: 48 81 d0 00 30 01 00 adcq $77824, %rax
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# DISASM-NEXT: 1103f: 48 81 c3 00 30 01 00 addq $77824, %rbx
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# DISASM-NEXT: 11046: 48 81 e1 00 30 01 00 andq $77824, %rcx
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# DISASM-NEXT: 1104d: 48 81 fa 00 30 01 00 cmpq $77824, %rdx
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# DISASM-NEXT: 11054: 48 81 cf 00 30 01 00 orq $77824, %rdi
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# DISASM-NEXT: 1105b: 48 81 de 00 30 01 00 sbbq $77824, %rsi
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# DISASM-NEXT: 11062: 48 81 ed 00 30 01 00 subq $77824, %rbp
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# DISASM-NEXT: 11069: 49 81 f0 00 30 01 00 xorq $77824, %r8
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# DISASM-NEXT: 11070: 49 f7 c7 00 30 01 00 testq $77824, %r15
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# RUN: ld.lld -shared %t.o -o %t2
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# RUN: llvm-readobj -s %t2 | FileCheck --check-prefix=SEC-PIC %s
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# RUN: llvm-objdump -d %t2 | FileCheck --check-prefix=DISASM-PIC %s
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# SEC-PIC: Section {
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# SEC-PIC: Index:
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# SEC-PIC: Name: .got
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# SEC-PIC-NEXT: Type: SHT_PROGBITS
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# SEC-PIC-NEXT: Flags [
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# SEC-PIC-NEXT: SHF_ALLOC
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# SEC-PIC-NEXT: SHF_WRITE
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# SEC-PIC-NEXT: ]
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# SEC-PIC-NEXT: Address: 0x2090
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# SEC-PIC-NEXT: Offset: 0x2090
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# SEC-PIC-NEXT: Size: 8
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# SEC-PIC-NEXT: Link:
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# SEC-PIC-NEXT: Info:
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# SEC-PIC-NEXT: AddressAlignment:
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# SEC-PIC-NEXT: EntrySize:
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# SEC-PIC-NEXT: }
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## Check that there was no relaxation performed. All values refer to got entry.
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## Ex: 0x1000 + 4234 + 6 = 0x2090
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## 0x102a + 4191 + 7 = 0x2090
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# DISASM-PIC: Disassembly of section .text:
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# DISASM-PIC-NEXT: _start:
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# DISASM-PIC-NEXT: 1000: 13 05 8a 10 00 00 adcl 4234(%rip), %eax
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# DISASM-PIC-NEXT: 1006: 03 1d 84 10 00 00 addl 4228(%rip), %ebx
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# DISASM-PIC-NEXT: 100c: 23 0d 7e 10 00 00 andl 4222(%rip), %ecx
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# DISASM-PIC-NEXT: 1012: 3b 15 78 10 00 00 cmpl 4216(%rip), %edx
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# DISASM-PIC-NEXT: 1018: 0b 35 72 10 00 00 orl 4210(%rip), %esi
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# DISASM-PIC-NEXT: 101e: 1b 3d 6c 10 00 00 sbbl 4204(%rip), %edi
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# DISASM-PIC-NEXT: 1024: 2b 2d 66 10 00 00 subl 4198(%rip), %ebp
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# DISASM-PIC-NEXT: 102a: 44 33 05 5f 10 00 00 xorl 4191(%rip), %r8d
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# DISASM-PIC-NEXT: 1031: 44 85 3d 58 10 00 00 testl 4184(%rip), %r15d
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# DISASM-PIC-NEXT: 1038: 48 13 05 51 10 00 00 adcq 4177(%rip), %rax
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# DISASM-PIC-NEXT: 103f: 48 03 1d 4a 10 00 00 addq 4170(%rip), %rbx
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# DISASM-PIC-NEXT: 1046: 48 23 0d 43 10 00 00 andq 4163(%rip), %rcx
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# DISASM-PIC-NEXT: 104d: 48 3b 15 3c 10 00 00 cmpq 4156(%rip), %rdx
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# DISASM-PIC-NEXT: 1054: 48 0b 3d 35 10 00 00 orq 4149(%rip), %rdi
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# DISASM-PIC-NEXT: 105b: 48 1b 35 2e 10 00 00 sbbq 4142(%rip), %rsi
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# DISASM-PIC-NEXT: 1062: 48 2b 2d 27 10 00 00 subq 4135(%rip), %rbp
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# DISASM-PIC-NEXT: 1069: 4c 33 05 20 10 00 00 xorq 4128(%rip), %r8
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# DISASM-PIC-NEXT: 1070: 4c 85 3d 19 10 00 00 testq 4121(%rip), %r15
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.data
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.type bar, @object
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bar:
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.byte 1
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.size bar, .-bar
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.text
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.globl _start
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.type _start, @function
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_start:
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adcl bar@GOTPCREL(%rip), %eax
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addl bar@GOTPCREL(%rip), %ebx
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andl bar@GOTPCREL(%rip), %ecx
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cmpl bar@GOTPCREL(%rip), %edx
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orl bar@GOTPCREL(%rip), %esi
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sbbl bar@GOTPCREL(%rip), %edi
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subl bar@GOTPCREL(%rip), %ebp
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xorl bar@GOTPCREL(%rip), %r8d
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testl %r15d, bar@GOTPCREL(%rip)
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adcq bar@GOTPCREL(%rip), %rax
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addq bar@GOTPCREL(%rip), %rbx
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andq bar@GOTPCREL(%rip), %rcx
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cmpq bar@GOTPCREL(%rip), %rdx
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orq bar@GOTPCREL(%rip), %rdi
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sbbq bar@GOTPCREL(%rip), %rsi
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subq bar@GOTPCREL(%rip), %rbp
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xorq bar@GOTPCREL(%rip), %r8
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testq %r15, bar@GOTPCREL(%rip)
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