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[AMDGPU] Fix VOPC instruction operand namings 

Differential Revision: http://reviews.llvm.org/D17966

llvm-svn: 263242
This commit is contained in:
Valery Pykhtin 2016-03-11 14:53:28 +00:00
parent 03f306c7c5
commit a7f480b4e9
2 changed files with 27 additions and 2 deletions
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4
llvm/lib/Target/AMDGPU/SIInstrFormats.td
View File

@ -445,10 +445,10 @@ class VOP3be <bits<9> op> : Enc64 {
class VOPCe <bits<8> op> : Enc32 {
bits<9> src0;
bits<8> vsrc1;
bits<8> src1;
let Inst{8-0} = src0;
let Inst{16-9} = vsrc1;
let Inst{16-9} = src1;
let Inst{24-17} = op;
let Inst{31-25} = 0x3e;
}

25
llvm/test/MC/Disassembler/AMDGPU/vopc_vi.txt Normal file
View File

@ -0,0 +1,25 @@
# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
# VI: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x82,0x7c]
0x02 0x08 0x82 0x7c
# VI: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x82,0x7c]
0x80 0x08 0x82 0x7c
# VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
0x02 0x09 0x82 0x7c
# VI: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7c]
0x02 0x09 0x80 0x7c
# VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
0x02 0x09 0x82 0x7c
# VI: v_cmp_f_f64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7c]
0x02 0x09 0xc0 0x7c
# VI: v_cmp_f_i32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7d]
0x02 0x09 0x80 0x7d
# VI: v_cmp_f_i64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7d]
0x02 0x09 0xc0 0x7d