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Support the "target" encodings for the CB[N]Z instructions. 

llvm-svn: 121308
This commit is contained in:
Bill Wendling 2010-12-08 23:01:43 +00:00
parent 7f3e9150d0
commit a7d6aa902a
7 changed files with 66 additions and 41 deletions
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1
llvm/lib/MC/ELFObjectWriter.cpp
View File

@ -1549,6 +1549,7 @@ unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target,
case ARM::fixup_arm_pcrel_10:
case ARM::fixup_arm_adr_pcrel_12:
case ARM::fixup_arm_thumb_bl:
case ARM::fixup_arm_thumb_br:
case ARM::fixup_arm_thumb_cp:
assert(0 && "Unimplemented"); break;
case ARM::fixup_arm_branch:

8
llvm/lib/Target/ARM/ARMAsmBackend.cpp
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@ -145,6 +145,11 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
// 'off by 4' is implicitly handled by the half-word ordering of the
// Thumb encoding, so we only need to adjust by 2 here.
return ((Value - 2) >> 2) & 0xff;
case ARM::fixup_arm_thumb_br: {
// Offset by 4 and don't encode the lower bit, which is always 0.
uint32_t Binary = (Value - 4) >> 1;
return ((Binary & 0x20) << 9) | ((Binary & 0x1f) << 3);
}
case ARM::fixup_arm_pcrel_10:
Value = Value - 6; // ARM fixups offset by an additional word and don't
// need to adjust for the half-word ordering.
@ -258,6 +263,9 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
case ARM::fixup_arm_thumb_cp:
return 1;
case ARM::fixup_arm_thumb_br:
return 2;
case ARM::fixup_arm_ldst_pcrel_12:
case ARM::fixup_arm_pcrel_10:
case ARM::fixup_arm_adr_pcrel_12:

2
llvm/lib/Target/ARM/ARMCodeEmitter.cpp
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@ -173,6 +173,8 @@ namespace {
const { return 0; }
unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)

4
llvm/lib/Target/ARM/ARMFixupKinds.h
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@ -31,9 +31,13 @@ enum Fixups {
// fixup_arm_branch - 24-bit PC relative relocation for direct branch
// instructions.
fixup_arm_branch,
// fixup_arm_thumb_bl - Fixup for Thumb BL/BLX instructions.
fixup_arm_thumb_bl,
// fixup_arm_thumb_br - Fixup for Thumb branch instructions.
fixup_arm_thumb_br,
// fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs.
fixup_arm_thumb_cp,

12
llvm/lib/Target/ARM/ARMInstrThumb.td
View File

@ -74,6 +74,10 @@ def t_imm_s4 : Operand<i32> {
// Define Thumb specific addressing modes.
def t_brtarget : Operand<i32> {
let EncoderMethod = "getThumbBRTargetOpValue";
}
def t_bltarget : Operand<i32> {
let EncoderMethod = "getThumbBLTargetOpValue";
}
@ -510,7 +514,7 @@ let isBranch = 1, isTerminator = 1 in
// Compare and branch on zero / non-zero
let isBranch = 1, isTerminator = 1 in {
def tCBZ : T1I<(outs), (ins tGPR:$Rn, brtarget:$target), IIC_Br,
def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_brtarget:$target), IIC_Br,
"cbz\t$Rn, $target", []>,
T1Misc<{0,0,?,1,?,?,?}> {
// A8.6.27
@ -521,7 +525,7 @@ let isBranch = 1, isTerminator = 1 in {
let Inst{2-0} = Rn;
}
def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_brtarget:$target), IIC_Br,
"cbnz\t$cmp, $target", []>,
T1Misc<{1,0,?,1,?,?,?}> {
// A8.6.27
@ -563,7 +567,7 @@ def tLDR : // A8.6.60
"ldr", "\t$Rt, $addr",
[(set tGPR:$Rt, (load t_addrmode_s4:$addr))]>;
def tLDRi: // A8.6.57
def tLDRi : // A8.6.57
T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
AddrModeT1_4, IIC_iLoad_r,
"ldr", "\t$Rt, $addr",
@ -587,7 +591,7 @@ def tLDRH : // A8.6.76
"ldrh", "\t$dst, $addr",
[(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
def tLDRHi: // A8.6.73
def tLDRHi : // A8.6.73
T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_s2:$addr),
AddrModeT1_2, IIC_iLoad_bh_r,
"ldrh", "\t$Rt, $addr",

77
llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
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@ -52,6 +52,7 @@ public:
{ "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_movt_hi16", 0, 16, 0 },
{ "fixup_arm_movw_lo16", 0, 16, 0 },
@ -89,6 +90,10 @@ public:
uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;
/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;
/// getBranchTargetOpValue - Return encoding info for 24-bit immediate
/// branch target.
uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
@ -412,54 +417,54 @@ EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
return isAdd;
}
/// getThumbBLTargetOpValue - Return encoding info for immediate
/// branch target.
/// getBranchTargetOpValue - Helper function to get the branch target operand,
/// which is either an immediate or requires a fixup.
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
unsigned FixupKind,
SmallVectorImpl<MCFixup> &Fixups) {
const MCOperand &MO = MI.getOperand(OpIdx);
// If the destination is an immediate, we have nothing to do.
if (MO.isImm()) return MO.getImm();
assert(MO.isExpr() && "Unexpected branch target type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(FixupKind);
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
// All of the information is in the fixup.
return 0;
}
/// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
uint32_t ARMMCCodeEmitter::
getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpIdx);
// If the destination is an immediate, we have nothing to do.
if (MO.isImm()) return MO.getImm();
assert (MO.isExpr() && "Unexpected branch target type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_thumb_bl);
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
// All of the information is in the fixup.
return 0;
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups);
}
/// getBranchTargetOpValue - Return encoding info for 24-bit immediate
/// branch target.
/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
uint32_t ARMMCCodeEmitter::
getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups);
}
/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
/// target.
uint32_t ARMMCCodeEmitter::
getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpIdx);
// If the destination is an immediate, we have nothing to do.
if (MO.isImm()) return MO.getImm();
assert (MO.isExpr() && "Unexpected branch target type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_branch);
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
// All of the information is in the fixup.
return 0;
SmallVectorImpl<MCFixup> &Fixups) const {
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_branch, Fixups);
}
/// getAdrLabelOpValue - Return encoding info for 12-bit immediate
/// ADR label target.
/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
/// target.
uint32_t ARMMCCodeEmitter::
getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpIdx);
assert (MO.isExpr() && "Unexpected adr target type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_adr_pcrel_12);
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
// All of the information is in the fixup.
return 0;
assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
Fixups);
}
/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.

3
llvm/utils/TableGen/EDEmitter.cpp
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@ -587,8 +587,9 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
IMM("neon_vcvt_imm32");
MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
MISC("t_bltarget", "kOperandTypeARMBranchTarget"); // ?
MISC("t_brtarget", "kOperandTypeARMBranchTarget"); // ?
MISC("bltarget", "kOperandTypeARMBranchTarget"); // ?
MISC("t_bltarget", "kOperandTypeARMBranchTarget"); // ?
MISC("so_reg", "kOperandTypeARMSoReg"); // R, R, I
MISC("shift_so_reg", "kOperandTypeARMSoReg"); // R, R, I
MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I