[SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV

Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D108973
2021-09-01 13:08:13 +08:00 · 2021-09-01 13:08:13 +08:00 · a78dd726f4
parent 199344d832
commit a78dd726f4
1 changed files with 4 additions and 0 deletions
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@ -73,6 +73,10 @@ public:
    llvm_unreachable("Unsupported register kind");
  }

+  unsigned getMinVectorRegisterBitWidth() const {
+    return ST->hasStdExtV() ? ST->getMinRVVVectorSizeInBits() : 0;
+  }
+
  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
                                         const Value *Ptr, bool VariableMask,
                                         Align Alignment,