Use multiclass for the load instructions with MEMri operand.
llvm-svn: 169018
This commit is contained in:
Jyotsna Verma
parent
1450ac6406
commit
a77c054e85
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@ -843,13 +843,72 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
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// LD +
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//===----------------------------------------------------------------------===//
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///
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///
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// Load doubleword.
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let isPredicable = 1 in
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def LDrid : LDInst<(outs DoubleRegs:$dst),
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(ins MEMri:$addr),
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"$dst = memd($addr)",
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[(set (i64 DoubleRegs:$dst), (i64 (load ADDRriS11_3:$addr)))]>;
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// Load -- MEMri operand
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multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
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bit isNot, bit isPredNew> {
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let PNewValue = #!if(isPredNew, "new", "") in
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def #NAME# : LDInst2<(outs RC:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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#!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#"$dst = "#mnemonic#"($addr)",
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[]>;
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}
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multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
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let PredSense = #!if(PredNot, "false", "true") in {
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defm _c#NAME# : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
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// Predicate new
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defm _cdn#NAME# : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
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}
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}
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let isExtendable = 1, neverHasSideEffects = 1 in
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multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
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bits<5> ImmBits, bits<5> PredImmBits> {
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let CextOpcode = CextOp, BaseOpcode = CextOp in {
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let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
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isPredicable = 1 in
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def #NAME# : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
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"$dst = "#mnemonic#"($addr)",
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[]>;
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let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
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isPredicated = 1 in {
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defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
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defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
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}
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}
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}
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let addrMode = BaseImmOffset, isMEMri = "true" in {
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defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
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defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
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defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
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defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
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defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
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defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
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}
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def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
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(LDrib ADDRriS11_0:$addr) >;
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def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
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(LDriub ADDRriS11_0:$addr) >;
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def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
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(LDrih ADDRriS11_1:$addr) >;
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def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
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(LDriuh ADDRriS11_1:$addr) >;
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def : Pat < (i32 (load ADDRriS11_2:$addr)),
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(LDriw ADDRriS11_2:$addr) >;
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def : Pat < (i64 (load ADDRriS11_3:$addr)),
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(LDrid ADDRriS11_3:$addr) >;
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let isPredicable = 1, AddedComplexity = 20 in
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def LDrid_indexed : LDInst<(outs DoubleRegs:$dst),
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@ -934,19 +993,6 @@ let hasCtrlDep = 1, neverHasSideEffects = 1 in {
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}
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// Load doubleword conditionally.
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrid_cPt : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if ($src1) $dst = memd($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrid_cNotPt : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if (!$src1) $dst = memd($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrid_indexed_cPt : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
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@ -959,18 +1005,6 @@ def LDrid_indexed_cNotPt : LDInst2<(outs DoubleRegs:$dst),
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"if (!$src1) $dst = memd($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrid_cdnPt : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if ($src1.new) $dst = memd($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrid_cdnNotPt : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if (!$src1.new) $dst = memd($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrid_indexed_cdnPt : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
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@ -983,14 +1017,6 @@ def LDrid_indexed_cdnNotPt : LDInst2<(outs DoubleRegs:$dst),
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"if (!$src1.new) $dst = memd($src2+#$src3)",
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[]>;
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// Load byte.
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let isPredicable = 1 in
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def LDrib : LDInst<(outs IntRegs:$dst),
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(ins MEMri:$addr),
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"$dst = memb($addr)",
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[(set (i32 IntRegs:$dst), (i32 (sextloadi8 ADDRriS11_0:$addr)))]>;
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// Load byte any-extend.
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def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
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(i32 (LDrib ADDRriS11_0:$addr)) >;
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@ -1031,18 +1057,6 @@ def LDub_GP : LDInst2<(outs IntRegs:$dst),
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Requires<[NoV4T]>;
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// Load byte conditionally.
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrib_cPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if ($src1) $dst = memb($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrib_cNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if (!$src1) $dst = memb($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrib_indexed_cPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
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@ -1055,18 +1069,6 @@ def LDrib_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
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"if (!$src1) $dst = memb($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrib_cdnPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if ($src1.new) $dst = memb($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrib_cdnNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if (!$src1.new) $dst = memb($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrib_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
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@ -1081,12 +1083,6 @@ def LDrib_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
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// Load halfword.
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let isPredicable = 1 in
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def LDrih : LDInst<(outs IntRegs:$dst),
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(ins MEMri:$addr),
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"$dst = memh($addr)",
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[(set (i32 IntRegs:$dst), (i32 (sextloadi16 ADDRriS11_1:$addr)))]>;
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let isPredicable = 1, AddedComplexity = 20 in
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def LDrih_indexed : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, s11_1Imm:$offset),
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@ -1124,18 +1120,6 @@ def LDuh_GP : LDInst2<(outs IntRegs:$dst),
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Requires<[NoV4T]>;
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// Load halfword conditionally.
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrih_cPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if ($src1) $dst = memh($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrih_cNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if (!$src1) $dst = memh($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrih_indexed_cPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
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@ -1148,18 +1132,6 @@ def LDrih_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
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"if (!$src1) $dst = memh($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrih_cdnPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if ($src1.new) $dst = memh($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrih_cdnNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if (!$src1.new) $dst = memh($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrih_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
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@ -1173,12 +1145,6 @@ def LDrih_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
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[]>;
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// Load unsigned byte.
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let isPredicable = 1 in
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def LDriub : LDInst<(outs IntRegs:$dst),
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(ins MEMri:$addr),
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"$dst = memub($addr)",
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[(set (i32 IntRegs:$dst), (i32 (zextloadi8 ADDRriS11_0:$addr)))]>;
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def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
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(i32 (LDriub ADDRriS11_0:$addr))>;
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@ -1202,18 +1168,6 @@ def LDriub_GP : LDInst2<(outs IntRegs:$dst),
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Requires<[NoV4T]>;
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// Load unsigned byte conditionally.
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriub_cPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if ($src1) $dst = memub($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriub_cNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if (!$src1) $dst = memub($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriub_indexed_cPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
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@ -1226,18 +1180,6 @@ def LDriub_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
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"if (!$src1) $dst = memub($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriub_cdnPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if ($src1.new) $dst = memub($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriub_cdnNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if (!$src1.new) $dst = memub($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriub_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
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@ -1251,12 +1193,6 @@ def LDriub_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
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[]>;
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// Load unsigned halfword.
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let isPredicable = 1 in
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def LDriuh : LDInst<(outs IntRegs:$dst),
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(ins MEMri:$addr),
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"$dst = memuh($addr)",
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[(set (i32 IntRegs:$dst), (i32 (zextloadi16 ADDRriS11_1:$addr)))]>;
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// Indexed load unsigned halfword.
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let isPredicable = 1, AddedComplexity = 20 in
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def LDriuh_indexed : LDInst<(outs IntRegs:$dst),
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@ -1274,18 +1210,6 @@ def LDriuh_GP : LDInst2<(outs IntRegs:$dst),
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Requires<[NoV4T]>;
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// Load unsigned halfword conditionally.
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriuh_cPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if ($src1) $dst = memuh($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriuh_cNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if (!$src1) $dst = memuh($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriuh_indexed_cPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
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@ -1298,18 +1222,6 @@ def LDriuh_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
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"if (!$src1) $dst = memuh($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriuh_cdnPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if ($src1.new) $dst = memuh($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriuh_cdnNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if (!$src1.new) $dst = memuh($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriuh_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
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@ -1324,11 +1236,6 @@ def LDriuh_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
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// Load word.
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let isPredicable = 1 in
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def LDriw : LDInst<(outs IntRegs:$dst),
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(ins MEMri:$addr), "$dst = memw($addr)",
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[(set IntRegs:$dst, (i32 (load ADDRriS11_2:$addr)))]>;
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// Load predicate.
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let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
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def LDriw_pred : LDInst<(outs PredRegs:$dst),
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@ -1359,19 +1266,6 @@ def LDw_GP : LDInst2<(outs IntRegs:$dst),
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Requires<[NoV4T]>;
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// Load word conditionally.
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriw_cPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if ($src1) $dst = memw($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriw_cNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if (!$src1) $dst = memw($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriw_indexed_cPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
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@ -1384,18 +1278,6 @@ def LDriw_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
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"if (!$src1) $dst = memw($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriw_cdnPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if ($src1.new) $dst = memw($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriw_cdnNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, MEMri:$addr),
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"if (!$src1.new) $dst = memw($addr)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriw_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
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Reference in New Issue