Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations,
now using shuffles instead of intrinsics. llvm-svn: 79673
This commit is contained in:
Bob Wilson
parent
f31a44ec01
commit
a70623102e
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@ -2403,6 +2403,53 @@ static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
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return true;
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}
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static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
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unsigned &WhichResult) {
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unsigned NumElts = VT.getVectorNumElements();
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WhichResult = (M[0] == 0 ? 0 : 1);
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for (unsigned i = 0; i < NumElts; i += 2) {
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if ((unsigned) M[i] != i + WhichResult ||
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(unsigned) M[i+1] != i + NumElts + WhichResult)
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return false;
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}
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return true;
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}
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static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
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unsigned &WhichResult) {
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unsigned NumElts = VT.getVectorNumElements();
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WhichResult = (M[0] == 0 ? 0 : 1);
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for (unsigned i = 0; i != NumElts; ++i) {
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if ((unsigned) M[i] != 2 * i + WhichResult)
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return false;
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}
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// VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
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if (VT.is64BitVector() && VT.getVectorElementType().getSizeInBits() == 32)
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return false;
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return true;
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}
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static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
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unsigned &WhichResult) {
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unsigned NumElts = VT.getVectorNumElements();
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WhichResult = (M[0] == 0 ? 0 : 1);
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unsigned Idx = WhichResult * NumElts / 2;
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for (unsigned i = 0; i != NumElts; i += 2) {
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if ((unsigned) M[i] != Idx ||
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(unsigned) M[i+1] != Idx + NumElts)
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return false;
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Idx += 1;
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}
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// VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
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if (VT.is64BitVector() && VT.getVectorElementType().getSizeInBits() == 32)
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return false;
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return true;
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}
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static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
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// Canonicalize all-zeros and all-ones vectors.
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ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
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@ -2504,13 +2551,16 @@ ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
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}
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bool ReverseVEXT;
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unsigned Imm;
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unsigned Imm, WhichResult;
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return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
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isVREVMask(M, VT, 64) ||
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isVREVMask(M, VT, 32) ||
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isVREVMask(M, VT, 16) ||
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isVEXTMask(M, VT, ReverseVEXT, Imm));
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isVEXTMask(M, VT, ReverseVEXT, Imm) ||
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isVTRNMask(M, VT, WhichResult) ||
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isVUZPMask(M, VT, WhichResult) ||
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isVZIPMask(M, VT, WhichResult));
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}
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/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
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@ -2610,11 +2660,9 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
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bool ReverseVEXT;
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unsigned Imm;
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if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
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SDValue Op0 = SVN->getOperand(0);
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SDValue Op1 = SVN->getOperand(1);
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if (ReverseVEXT)
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std::swap(Op0, Op1);
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return DAG.getNode(ARMISD::VEXT, dl, VT, Op0, Op1,
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std::swap(V1, V2);
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return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
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DAG.getConstant(Imm, MVT::i32));
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}
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@ -2625,6 +2673,24 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
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if (isVREVMask(ShuffleMask, VT, 16))
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return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
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// Check for Neon shuffles that modify both input vectors in place.
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// If both results are used, i.e., if there are two shuffles with the same
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// source operands and with masks corresponding to both results of one of
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// these operations, DAG memoization will ensure that a single node is
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// used for both shuffles.
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unsigned WhichResult;
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if (isVTRNMask(ShuffleMask, VT, WhichResult))
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return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
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V1, V2).getValue(WhichResult);
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if (isVUZPMask(ShuffleMask, VT, WhichResult))
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return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
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V1, V2).getValue(WhichResult);
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if (isVZIPMask(ShuffleMask, VT, WhichResult))
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return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
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V1, V2).getValue(WhichResult);
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// If the shuffle is not directly supported and it has 4 elements, use
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// the PerfectShuffle-generated table to synthesize it from other shuffles.
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if (VT.getVectorNumElements() == 4 &&
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(VT.is128BitVector() || VT.is64BitVector())) {
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unsigned PFIndexes[4];
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@ -132,9 +132,8 @@ namespace llvm {
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VREV64, // reverse elements within 64-bit doublewords
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VREV32, // reverse elements within 32-bit words
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VREV16, // reverse elements within 16-bit halfwords
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VZIP, // zip
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VUZP, // unzip
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VZIP, // zip (interleave)
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VUZP, // unzip (deinterleave)
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VTRN // transpose
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};
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}
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@ -0,0 +1,99 @@
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; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
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%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
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%struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
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%struct.__builtin_neon_v2si2 = type { <2 x i32>, <2 x i32> }
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%struct.__builtin_neon_v2sf2 = type { <2 x float>, <2 x float> }
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%struct.__builtin_neon_v16qi2 = type { <16 x i8>, <16 x i8> }
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%struct.__builtin_neon_v8hi2 = type { <8 x i16>, <8 x i16> }
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%struct.__builtin_neon_v4si2 = type { <4 x i32>, <4 x i32> }
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%struct.__builtin_neon_v4sf2 = type { <4 x float>, <4 x float> }
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define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vtrni8:
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;CHECK: vtrn.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
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%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
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%tmp5 = add <8 x i8> %tmp3, %tmp4
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ret <8 x i8> %tmp5
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}
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define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vtrni16:
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;CHECK: vtrn.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%tmp5 = add <4 x i16> %tmp3, %tmp4
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ret <4 x i16> %tmp5
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}
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define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vtrni32:
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;CHECK: vtrn.32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>
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%tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>
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%tmp5 = add <2 x i32> %tmp3, %tmp4
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ret <2 x i32> %tmp5
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}
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define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK: vtrnf:
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;CHECK: vtrn.32
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2>
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%tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3>
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%tmp5 = add <2 x float> %tmp3, %tmp4
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ret <2 x float> %tmp5
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}
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define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vtrnQi8:
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;CHECK: vtrn.8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
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%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
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%tmp5 = add <16 x i8> %tmp3, %tmp4
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ret <16 x i8> %tmp5
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}
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define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vtrnQi16:
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;CHECK: vtrn.16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
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%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
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%tmp5 = add <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vtrnQi32:
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;CHECK: vtrn.32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%tmp5 = add <4 x i32> %tmp3, %tmp4
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ret <4 x i32> %tmp5
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}
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define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK: vtrnQf:
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;CHECK: vtrn.32
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%tmp5 = add <4 x float> %tmp3, %tmp4
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ret <4 x float> %tmp5
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}
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@ -0,0 +1,79 @@
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; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
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%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
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%struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
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%struct.__builtin_neon_v2si2 = type { <2 x i32>, <2 x i32> }
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%struct.__builtin_neon_v2sf2 = type { <2 x float>, <2 x float> }
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%struct.__builtin_neon_v16qi2 = type { <16 x i8>, <16 x i8> }
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%struct.__builtin_neon_v8hi2 = type { <8 x i16>, <8 x i16> }
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%struct.__builtin_neon_v4si2 = type { <4 x i32>, <4 x i32> }
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%struct.__builtin_neon_v4sf2 = type { <4 x float>, <4 x float> }
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define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vuzpi8:
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;CHECK: vuzp.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%tmp5 = add <8 x i8> %tmp3, %tmp4
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ret <8 x i8> %tmp5
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}
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define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vuzpi16:
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;CHECK: vuzp.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%tmp5 = add <4 x i16> %tmp3, %tmp4
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ret <4 x i16> %tmp5
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}
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; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
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define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vuzpQi8:
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;CHECK: vuzp.8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
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%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
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%tmp5 = add <16 x i8> %tmp3, %tmp4
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ret <16 x i8> %tmp5
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}
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define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vuzpQi16:
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;CHECK: vuzp.16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%tmp5 = add <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vuzpQi32:
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;CHECK: vuzp.32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%tmp5 = add <4 x i32> %tmp3, %tmp4
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ret <4 x i32> %tmp5
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}
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define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK: vuzpQf:
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;CHECK: vuzp.32
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%tmp5 = add <4 x float> %tmp3, %tmp4
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ret <4 x float> %tmp5
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}
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@ -0,0 +1,79 @@
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; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
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%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
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%struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
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%struct.__builtin_neon_v2si2 = type { <2 x i32>, <2 x i32> }
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%struct.__builtin_neon_v2sf2 = type { <2 x float>, <2 x float> }
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%struct.__builtin_neon_v16qi2 = type { <16 x i8>, <16 x i8> }
|
||||
%struct.__builtin_neon_v8hi2 = type { <8 x i16>, <8 x i16> }
|
||||
%struct.__builtin_neon_v4si2 = type { <4 x i32>, <4 x i32> }
|
||||
%struct.__builtin_neon_v4sf2 = type { <4 x float>, <4 x float> }
|
||||
|
||||
define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK: vzipi8:
|
||||
;CHECK: vzip.8
|
||||
%tmp1 = load <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
|
||||
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
|
||||
%tmp5 = add <8 x i8> %tmp3, %tmp4
|
||||
ret <8 x i8> %tmp5
|
||||
}
|
||||
|
||||
define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
;CHECK: vzipi16:
|
||||
;CHECK: vzip.16
|
||||
%tmp1 = load <4 x i16>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
|
||||
%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
|
||||
%tmp5 = add <4 x i16> %tmp3, %tmp4
|
||||
ret <4 x i16> %tmp5
|
||||
}
|
||||
|
||||
; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
|
||||
|
||||
define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
|
||||
;CHECK: vzipQi8:
|
||||
;CHECK: vzip.8
|
||||
%tmp1 = load <16 x i8>* %A
|
||||
%tmp2 = load <16 x i8>* %B
|
||||
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
|
||||
%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
|
||||
%tmp5 = add <16 x i8> %tmp3, %tmp4
|
||||
ret <16 x i8> %tmp5
|
||||
}
|
||||
|
||||
define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
|
||||
;CHECK: vzipQi16:
|
||||
;CHECK: vzip.16
|
||||
%tmp1 = load <8 x i16>* %A
|
||||
%tmp2 = load <8 x i16>* %B
|
||||
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
|
||||
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
|
||||
%tmp5 = add <8 x i16> %tmp3, %tmp4
|
||||
ret <8 x i16> %tmp5
|
||||
}
|
||||
|
||||
define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
|
||||
;CHECK: vzipQi32:
|
||||
;CHECK: vzip.32
|
||||
%tmp1 = load <4 x i32>* %A
|
||||
%tmp2 = load <4 x i32>* %B
|
||||
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
|
||||
%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
|
||||
%tmp5 = add <4 x i32> %tmp3, %tmp4
|
||||
ret <4 x i32> %tmp5
|
||||
}
|
||||
|
||||
define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
|
||||
;CHECK: vzipQf:
|
||||
;CHECK: vzip.32
|
||||
%tmp1 = load <4 x float>* %A
|
||||
%tmp2 = load <4 x float>* %B
|
||||
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
|
||||
%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
|
||||
%tmp5 = add <4 x float> %tmp3, %tmp4
|
||||
ret <4 x float> %tmp5
|
||||
}
|
||||
Loading…
Reference in New Issue