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[InstCombine] Extend (add (sext x), cst) --> (sext (add x, cst')) and (add (zext x), cst) --> (zext (add x, cst')) to work for vectors 

Differential Revision: https://reviews.llvm.org/D51236

llvm-svn: 340796
This commit is contained in:
Craig Topper 2018-08-28 02:02:29 +00:00
parent 7c80f98b69
commit a6cd4b9bce
2 changed files with 18 additions and 16 deletions
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6
llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
View File

@ -1195,7 +1195,8 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) {
// integer add followed by a sext.
if (SExtInst *LHSConv = dyn_cast<SExtInst>(LHS)) {
// (add (sext x), cst) --> (sext (add x, cst'))
if (ConstantInt *RHSC = dyn_cast<ConstantInt>(RHS)) {
Constant *RHSC;
if (match(RHS, m_Constant(RHSC))) {
if (LHSConv->hasOneUse()) {
Constant *CI =
ConstantExpr::getTrunc(RHSC, LHSConv->getOperand(0)->getType());
@ -1231,7 +1232,8 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) {
// integer add followed by a zext.
if (auto *LHSConv = dyn_cast<ZExtInst>(LHS)) {
// (add (zext x), cst) --> (zext (add x, cst'))
if (ConstantInt *RHSC = dyn_cast<ConstantInt>(RHS)) {
Constant *RHSC;
if (match(RHS, m_Constant(RHSC))) {
if (LHSConv->hasOneUse()) {
Constant *CI =
ConstantExpr::getTrunc(RHSC, LHSConv->getOperand(0)->getType());

28
llvm/test/Transforms/InstCombine/sink-zext.ll
View File

@ -84,8 +84,8 @@ define i64 @test5(i32 %V) {
define <2 x i64> @test5_splat(<2 x i32> %V) {
; CHECK-LABEL: @test5_splat(
; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 1, i32 1>
; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i64> [[SEXT]], <i64 1073741823, i64 1073741823>
; CHECK-NEXT: [[ADDCONV:%.*]] = add nsw <2 x i32> [[ASHR]], <i32 1073741823, i32 1073741823>
; CHECK-NEXT: [[ADD:%.*]] = sext <2 x i32> [[ADDCONV]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[ADD]]
;
%ashr = ashr <2 x i32> %V, <i32 1, i32 1>
@ -97,8 +97,8 @@ define <2 x i64> @test5_splat(<2 x i32> %V) {
define <2 x i64> @test5_vec(<2 x i32> %V) {
; CHECK-LABEL: @test5_vec(
; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 1, i32 1>
; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i64> [[SEXT]], <i64 1, i64 2>
; CHECK-NEXT: [[ADDCONV:%.*]] = add nsw <2 x i32> [[ASHR]], <i32 1, i32 2>
; CHECK-NEXT: [[ADD:%.*]] = sext <2 x i32> [[ADDCONV]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[ADD]]
;
%ashr = ashr <2 x i32> %V, <i32 1, i32 1>
@ -123,8 +123,8 @@ define i64 @test6(i32 %V) {
define <2 x i64> @test6_splat(<2 x i32> %V) {
; CHECK-LABEL: @test6_splat(
; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 1, i32 1>
; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i64> [[SEXT]], <i64 -1073741824, i64 -1073741824>
; CHECK-NEXT: [[ADDCONV:%.*]] = add nsw <2 x i32> [[ASHR]], <i32 -1073741824, i32 -1073741824>
; CHECK-NEXT: [[ADD:%.*]] = sext <2 x i32> [[ADDCONV]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[ADD]]
;
%ashr = ashr <2 x i32> %V, <i32 1, i32 1>
@ -136,8 +136,8 @@ define <2 x i64> @test6_splat(<2 x i32> %V) {
define <2 x i64> @test6_vec(<2 x i32> %V) {
; CHECK-LABEL: @test6_vec(
; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 1, i32 1>
; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i64> [[SEXT]], <i64 -1, i64 -2>
; CHECK-NEXT: [[ADDCONV:%.*]] = add nsw <2 x i32> [[ASHR]], <i32 -1, i32 -2>
; CHECK-NEXT: [[ADD:%.*]] = sext <2 x i32> [[ADDCONV]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[ADD]]
;
%ashr = ashr <2 x i32> %V, <i32 1, i32 1>
@ -149,8 +149,8 @@ define <2 x i64> @test6_vec(<2 x i32> %V) {
define <2 x i64> @test6_vec2(<2 x i32> %V) {
; CHECK-LABEL: @test6_vec2(
; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 1, i32 1>
; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i64> [[SEXT]], <i64 -1, i64 1>
; CHECK-NEXT: [[ADDCONV:%.*]] = add nsw <2 x i32> [[ASHR]], <i32 -1, i32 1>
; CHECK-NEXT: [[ADD:%.*]] = sext <2 x i32> [[ADDCONV]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[ADD]]
;
%ashr = ashr <2 x i32> %V, <i32 1, i32 1>
@ -175,8 +175,8 @@ define i64 @test7(i32 %V) {
define <2 x i64> @test7_splat(<2 x i32> %V) {
; CHECK-LABEL: @test7_splat(
; CHECK-NEXT: [[LSHR:%.*]] = lshr <2 x i32> [[V:%.*]], <i32 1, i32 1>
; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[LSHR]] to <2 x i64>
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw <2 x i64> [[ZEXT]], <i64 2147483647, i64 2147483647>
; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw <2 x i32> [[LSHR]], <i32 2147483647, i32 2147483647>
; CHECK-NEXT: [[ADD:%.*]] = zext <2 x i32> [[ADDCONV]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[ADD]]
;
%lshr = lshr <2 x i32> %V, <i32 1, i32 1>
@ -188,8 +188,8 @@ define <2 x i64> @test7_splat(<2 x i32> %V) {
define <2 x i64> @test7_vec(<2 x i32> %V) {
; CHECK-LABEL: @test7_vec(
; CHECK-NEXT: [[LSHR:%.*]] = lshr <2 x i32> [[V:%.*]], <i32 1, i32 1>
; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[LSHR]] to <2 x i64>
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw <2 x i64> [[ZEXT]], <i64 1, i64 2>
; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw <2 x i32> [[LSHR]], <i32 1, i32 2>
; CHECK-NEXT: [[ADD:%.*]] = zext <2 x i32> [[ADDCONV]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[ADD]]
;
%lshr = lshr <2 x i32> %V, <i32 1, i32 1>