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Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whether 

or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and
PseudoSE (mips32/64 pseudo) classes.

llvm-svn: 161071
This commit is contained in:
Akira Hatanaka 2012-07-31 19:13:07 +00:00
parent fb4263f156
commit a66d676b20
4 changed files with 33 additions and 38 deletions
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12
llvm/lib/Target/Mips/Mips16InstrInfo.td
View File

@ -249,18 +249,6 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
hasExtraSrcRegAllocReq = 1 in hasExtraSrcRegAllocReq = 1 in
def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
// As stack alignment is always done with addiu, we need a 16-bit immediate
// This is basically deprecated code but needs to be there for things
// to work.
let Defs = [SP], Uses = [SP] in {
def ADJCALLSTACKDOWN16 : MipsPseudo16<(outs), (ins uimm16:$amt),
";",
[(callseq_start timm:$amt)]>;
def ADJCALLSTACKUP16 : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2),
";",
[(callseq_end timm:$amt1, timm:$amt2)]>;
}
// Small immediates // Small immediates
def : Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; def : Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;

16
llvm/lib/Target/Mips/MipsInstrFPU.td
View File

@ -416,25 +416,23 @@ let Defs=[FCR31] in {
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Floating Point Pseudo-Instructions // Floating Point Pseudo-Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src), def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCR:$src),
"# MOVCCRToCCR", []>; "# MOVCCRToCCR", []>;
// This pseudo instr gets expanded into 2 mtc1 instrs after register // This pseudo instr gets expanded into 2 mtc1 instrs after register
// allocation. // allocation.
def BuildPairF64 : def BuildPairF64 :
MipsPseudo<(outs AFGR64:$dst), PseudoSE<(outs AFGR64:$dst),
(ins CPURegs:$lo, CPURegs:$hi), "", (ins CPURegs:$lo, CPURegs:$hi), "",
[(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>; [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
// This pseudo instr gets expanded into 2 mfc1 instrs after register // This pseudo instr gets expanded into 2 mfc1 instrs after register
// allocation. // allocation.
// if n is 0, lower part of src is extracted. // if n is 0, lower part of src is extracted.
// if n is 1, higher part of src is extracted. // if n is 1, higher part of src is extracted.
def ExtractElementF64 : def ExtractElementF64 :
MipsPseudo<(outs CPURegs:$dst), PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n), "",
(ins AFGR64:$src, i32imm:$n), "", [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
[(set CPURegs:$dst,
(MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Floating Point Patterns // Floating Point Patterns

18
llvm/lib/Target/Mips/MipsInstrFormats.td
View File

@ -37,8 +37,8 @@ def FrmFI : Format<5>;
def FrmOther : Format<6>; // Instruction w/ a custom format def FrmOther : Format<6>; // Instruction w/ a custom format
// Generic Mips Format // Generic Mips Format
class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern, class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin, Format f>: Instruction InstrItinClass itin, Format f>: Instruction
{ {
field bits<32> Inst; field bits<32> Inst;
Format Form = f; Format Form = f;
@ -70,18 +70,28 @@ class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
let DecoderNamespace = "Mips"; let DecoderNamespace = "Mips";
field bits<32> SoftFail = 0; field bits<32> SoftFail = 0;
}
// Mips32/64 Instruction Format
class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin, Format f>:
MipsInst<outs, ins, asmstr, pattern, itin, f> {
let Predicates = [HasStandardEncoding]; let Predicates = [HasStandardEncoding];
} }
// Mips Pseudo Instructions Format // Mips Pseudo Instructions Format
class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>: class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
InstSE<outs, ins, asmstr, pattern, IIPseudo, Pseudo> { MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> {
let isCodeGenOnly = 1; let isCodeGenOnly = 1;
let isPseudo = 1; let isPseudo = 1;
} }
// Mips32/64 Pseudo Instruction Format
class PseudoSE<dag outs, dag ins, string asmstr, list<dag> pattern>:
MipsPseudo<outs, ins, asmstr, pattern> {
let Predicates = [HasStandardEncoding];
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

25
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -803,9 +803,9 @@ class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC, class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
RegisterClass PRC> : RegisterClass PRC> :
MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
!strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"), !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
[(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
multiclass Atomic2Ops32<PatFrag Op, string Opstr> { multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>,
@ -819,9 +819,9 @@ multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
// Atomic Compare & Swap. // Atomic Compare & Swap.
class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC, class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
RegisterClass PRC> : RegisterClass PRC> :
MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
!strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"), !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
[(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
multiclass AtomicCmpSwap32<PatFrag Op, string Width> { multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>,
@ -851,14 +851,13 @@ class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
// Return RA. // Return RA.
let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
def RetRA : MipsPseudo<(outs), (ins), "", [(MipsRet)]>; def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>;
// As stack alignment is always done with addiu, we need a 16-bit immediate let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
let Defs = [SP], Uses = [SP] in { def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
"!ADJCALLSTACKDOWN $amt", "!ADJCALLSTACKDOWN $amt",
[(callseq_start timm:$amt)]>; [(callseq_start timm:$amt)]>;
def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2), def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
"!ADJCALLSTACKUP $amt1", "!ADJCALLSTACKUP $amt1",
[(callseq_end timm:$amt1, timm:$amt2)]>; [(callseq_end timm:$amt1, timm:$amt2)]>;
} }
@ -868,8 +867,8 @@ def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
// are used, we have the same behavior, but get also a bunch of warnings // are used, we have the same behavior, but get also a bunch of warnings
// from the assembler. // from the assembler.
let neverHasSideEffects = 1 in let neverHasSideEffects = 1 in
def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc, CPURegs:$gp), def CPRESTORE : PseudoSE<(outs), (ins i32imm:$loc, CPURegs:$gp),
".cprestore\t$loc", []>; ".cprestore\t$loc", []>;
let usesCustomInserter = 1 in { let usesCustomInserter = 1 in {
defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">; defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;