Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whether
or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and PseudoSE (mips32/64 pseudo) classes. llvm-svn: 161071
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@ -249,18 +249,6 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
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hasExtraSrcRegAllocReq = 1 in
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hasExtraSrcRegAllocReq = 1 in
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def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
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def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
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// As stack alignment is always done with addiu, we need a 16-bit immediate
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// This is basically deprecated code but needs to be there for things
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// to work.
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let Defs = [SP], Uses = [SP] in {
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def ADJCALLSTACKDOWN16 : MipsPseudo16<(outs), (ins uimm16:$amt),
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";",
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[(callseq_start timm:$amt)]>;
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def ADJCALLSTACKUP16 : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2),
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";",
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[(callseq_end timm:$amt1, timm:$amt2)]>;
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}
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// Small immediates
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// Small immediates
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def : Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
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def : Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
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@ -416,13 +416,13 @@ let Defs=[FCR31] in {
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Floating Point Pseudo-Instructions
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// Floating Point Pseudo-Instructions
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src),
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def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCR:$src),
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"# MOVCCRToCCR", []>;
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"# MOVCCRToCCR", []>;
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// This pseudo instr gets expanded into 2 mtc1 instrs after register
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// This pseudo instr gets expanded into 2 mtc1 instrs after register
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// allocation.
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// allocation.
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def BuildPairF64 :
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def BuildPairF64 :
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MipsPseudo<(outs AFGR64:$dst),
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PseudoSE<(outs AFGR64:$dst),
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(ins CPURegs:$lo, CPURegs:$hi), "",
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(ins CPURegs:$lo, CPURegs:$hi), "",
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[(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
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[(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
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@ -431,10 +431,8 @@ def BuildPairF64 :
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// if n is 0, lower part of src is extracted.
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// if n is 0, lower part of src is extracted.
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// if n is 1, higher part of src is extracted.
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// if n is 1, higher part of src is extracted.
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def ExtractElementF64 :
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def ExtractElementF64 :
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MipsPseudo<(outs CPURegs:$dst),
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PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n), "",
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(ins AFGR64:$src, i32imm:$n), "",
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[(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
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[(set CPURegs:$dst,
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(MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Floating Point Patterns
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// Floating Point Patterns
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@ -37,7 +37,7 @@ def FrmFI : Format<5>;
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def FrmOther : Format<6>; // Instruction w/ a custom format
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def FrmOther : Format<6>; // Instruction w/ a custom format
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// Generic Mips Format
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// Generic Mips Format
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class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
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class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format f>: Instruction
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InstrItinClass itin, Format f>: Instruction
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{
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{
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field bits<32> Inst;
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field bits<32> Inst;
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@ -70,18 +70,28 @@ class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
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let DecoderNamespace = "Mips";
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let DecoderNamespace = "Mips";
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field bits<32> SoftFail = 0;
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field bits<32> SoftFail = 0;
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}
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// Mips32/64 Instruction Format
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class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format f>:
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MipsInst<outs, ins, asmstr, pattern, itin, f> {
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let Predicates = [HasStandardEncoding];
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let Predicates = [HasStandardEncoding];
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}
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}
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// Mips Pseudo Instructions Format
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// Mips Pseudo Instructions Format
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class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
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class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
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InstSE<outs, ins, asmstr, pattern, IIPseudo, Pseudo> {
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MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> {
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let isCodeGenOnly = 1;
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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let isPseudo = 1;
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}
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}
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// Mips32/64 Pseudo Instruction Format
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class PseudoSE<dag outs, dag ins, string asmstr, list<dag> pattern>:
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MipsPseudo<outs, ins, asmstr, pattern> {
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let Predicates = [HasStandardEncoding];
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
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// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -803,7 +803,7 @@ class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
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// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
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// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
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class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
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class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
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RegisterClass PRC> :
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RegisterClass PRC> :
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MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
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PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
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!strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
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!strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
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[(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
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[(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
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@ -819,7 +819,7 @@ multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
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// Atomic Compare & Swap.
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// Atomic Compare & Swap.
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class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
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class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
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RegisterClass PRC> :
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RegisterClass PRC> :
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MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
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PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
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!strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
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!strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
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[(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
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[(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
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@ -851,14 +851,13 @@ class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
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// Return RA.
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// Return RA.
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let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
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let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
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def RetRA : MipsPseudo<(outs), (ins), "", [(MipsRet)]>;
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def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>;
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// As stack alignment is always done with addiu, we need a 16-bit immediate
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let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
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let Defs = [SP], Uses = [SP] in {
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def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
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def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
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"!ADJCALLSTACKDOWN $amt",
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start timm:$amt)]>;
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[(callseq_start timm:$amt)]>;
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def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
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def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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"!ADJCALLSTACKUP $amt1",
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"!ADJCALLSTACKUP $amt1",
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[(callseq_end timm:$amt1, timm:$amt2)]>;
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[(callseq_end timm:$amt1, timm:$amt2)]>;
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}
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}
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@ -868,7 +867,7 @@ def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
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// are used, we have the same behavior, but get also a bunch of warnings
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// are used, we have the same behavior, but get also a bunch of warnings
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// from the assembler.
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// from the assembler.
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let neverHasSideEffects = 1 in
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let neverHasSideEffects = 1 in
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def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc, CPURegs:$gp),
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def CPRESTORE : PseudoSE<(outs), (ins i32imm:$loc, CPURegs:$gp),
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".cprestore\t$loc", []>;
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".cprestore\t$loc", []>;
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let usesCustomInserter = 1 in {
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let usesCustomInserter = 1 in {
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