Expose the logic for field address codegen; it is needed for aggregate
initializers, and I don't want to duplicate the bitfield-handling code. (I'll send a patch for aggregate initializers to the mailing list sometime soon.) llvm-svn: 46904
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@ -454,7 +454,6 @@ EmitOCUVectorElementExpr(const OCUVectorElementExpr *E) {
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}
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LValue CodeGenFunction::EmitMemberExpr(const MemberExpr *E) {
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llvm::Value *V;
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bool isUnion = false;
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Expr *BaseExpr = E->getBase();
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llvm::Value *BaseValue = NULL;
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@ -476,8 +475,15 @@ LValue CodeGenFunction::EmitMemberExpr(const MemberExpr *E) {
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}
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FieldDecl *Field = E->getMemberDecl();
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unsigned idx = CGM.getTypes().getLLVMFieldNo(Field);
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return EmitLValueForField(BaseValue, Field, isUnion);
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}
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LValue CodeGenFunction::EmitLValueForField(llvm::Value* BaseValue,
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FieldDecl* Field,
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bool isUnion)
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{
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llvm::Value *V;
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unsigned idx = CGM.getTypes().getLLVMFieldNo(Field);
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if (Field->isBitField()) {
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const llvm::Type * FieldTy = ConvertType(Field->getType());
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@ -568,7 +574,7 @@ RValue CodeGenFunction::EmitCallExpr(llvm::Value *Callee, QualType FnType,
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for (unsigned i = 0, e = NumArgs; i != e; ++i) {
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QualType ArgTy = ArgExprs[i]->getType();
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if (!hasAggregateLLVMType(ArgTy)) {
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// Scalar argument is passed by-value.
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Args.push_back(EmitScalarExpr(ArgExprs[i]));
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@ -71,6 +71,7 @@ namespace clang {
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class BlockVarDecl;
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class EnumConstantDecl;
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class ParmVarDecl;
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class FieldDecl;
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namespace CodeGen {
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class CodeGenModule;
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class CodeGenTypes;
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@ -415,6 +416,9 @@ public:
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LValue EmitArraySubscriptExpr(const ArraySubscriptExpr *E);
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LValue EmitOCUVectorElementExpr(const OCUVectorElementExpr *E);
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LValue EmitMemberExpr(const MemberExpr *E);
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LValue EmitLValueForField(llvm::Value* Base, FieldDecl* Field,
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bool isUnion);
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//===--------------------------------------------------------------------===//
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// Scalar Expression Emission
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