[AMDGPU] Do not allow register coalescer to create big superregs
Limit register coalescer by not allowing it to artificially increase size of registers beyond dword. Such super-registers are in fact register sequences and not distinct HW registers. With more super-regs we would need to allocate adjacent registers and constraint regalloc more than needed. Moreover, our super registers are overlapping. For instance we have VGPR0_VGPR1_VGPR2, VGPR1_VGPR2_VGPR3, VGPR2_VGPR3_VGPR4 etc, which complicates registers allocation even more, resulting in excessive spilling. Differential Revision: https://reviews.llvm.org/D28782 llvm-svn: 292413
This commit is contained in:
Stanislav Mekhanoshin
parent
fde0104649
commit
a4e63ead4b
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@ -1474,3 +1474,23 @@ bool SIRegisterInfo::isVGPR(const MachineRegisterInfo &MRI,
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unsigned Reg) const {
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return hasVGPRs(getRegClassForReg(MRI, Reg));
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}
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bool SIRegisterInfo::shouldCoalesce(MachineInstr *MI,
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const TargetRegisterClass *SrcRC,
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unsigned SubReg,
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const TargetRegisterClass *DstRC,
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unsigned DstSubReg,
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const TargetRegisterClass *NewRC) const {
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unsigned SrcSize = SrcRC->getSize();
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unsigned DstSize = DstRC->getSize();
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unsigned NewSize = NewRC->getSize();
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// Do not increase size of registers beyond dword, we would need to allocate
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// adjacent registers and constraint regalloc more than needed.
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// Always allow dword coalescing.
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if (SrcSize <= 4 || DstSize <= 4)
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return true;
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return NewSize <= DstSize || NewSize <= SrcSize;
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}
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@ -264,6 +264,13 @@ public:
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ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC,
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unsigned EltSize) const;
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bool shouldCoalesce(MachineInstr *MI,
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const TargetRegisterClass *SrcRC,
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unsigned SubReg,
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const TargetRegisterClass *DstRC,
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unsigned DstSubReg,
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const TargetRegisterClass *NewRC) const override;
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private:
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void buildSpillLoadStore(MachineBasicBlock::iterator MI,
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unsigned LoadStoreOp,
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@ -399,15 +399,15 @@ define void @global_extload_v2f16_to_v2f64(<2 x double> addrspace(1)* %out, <2 x
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; XVI-NOT: v_cvt_f32_f16
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; GCN: buffer_load_dwordx2 v{{\[}}[[IN_LO:[0-9]+]]:[[IN_HI:[0-9]+]]
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; VI: v_lshrrev_b32_e32 [[Y16:v[0-9]+]], 16, v[[IN_LO]]
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; GCN: v_cvt_f32_f16_e32 [[Z32:v[0-9]+]], v[[IN_HI]]
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; GCN: v_cvt_f32_f16_e32 [[X32:v[0-9]+]], v[[IN_LO]]
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; SI: v_lshrrev_b32_e32 [[Y16:v[0-9]+]], 16, v[[IN_LO]]
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; GCN: v_cvt_f32_f16_e32 [[Y32:v[0-9]+]], [[Y16]]
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; VI-DAG: v_lshrrev_b32_e32 [[Y16:v[0-9]+]], 16, v[[IN_LO]]
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; GCN-DAG: v_cvt_f32_f16_e32 [[Z32:v[0-9]+]], v[[IN_HI]]
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; GCN-DAG: v_cvt_f32_f16_e32 [[X32:v[0-9]+]], v[[IN_LO]]
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; SI: v_lshrrev_b32_e32 [[Y16:v[0-9]+]], 16, v[[IN_LO]]
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; GCN-DAG: v_cvt_f32_f16_e32 [[Y32:v[0-9]+]], [[Y16]]
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; GCN: v_cvt_f64_f32_e32 [[Z:v\[[0-9]+:[0-9]+\]]], [[Z32]]
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; GCN: v_cvt_f64_f32_e32 v{{\[}}[[XLO:[0-9]+]]:{{[0-9]+}}], [[X32]]
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; GCN: v_cvt_f64_f32_e32 v[{{[0-9]+}}:[[YHI:[0-9]+]]{{\]}}, [[Y32]]
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; GCN-DAG: v_cvt_f64_f32_e32 [[Z:v\[[0-9]+:[0-9]+\]]], [[Z32]]
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; GCN-DAG: v_cvt_f64_f32_e32 v{{\[}}[[XLO:[0-9]+]]:{{[0-9]+}}], [[X32]]
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; GCN-DAG: v_cvt_f64_f32_e32 v[{{[0-9]+}}:[[YHI:[0-9]+]]{{\]}}, [[Y32]]
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; GCN-NOT: v_cvt_f64_f32_e32
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; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[XLO]]:[[YHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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@ -0,0 +1,71 @@
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# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck %s
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# Check that coalescer does not create wider register tuple than in source
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# CHECK: - { id: 2, class: vreg_64 }
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# CHECK: - { id: 3, class: vreg_64 }
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# CHECK: - { id: 4, class: vreg_64 }
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# CHECK: - { id: 5, class: vreg_96 }
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# CHECK: - { id: 6, class: vreg_96 }
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# CHECK: - { id: 7, class: vreg_128 }
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# CHECK: - { id: 8, class: vreg_128 }
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# No more registers shall be defined
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# CHECK-NEXT: liveins:
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# CHECK: FLAT_STORE_DWORDX2 %vgpr0_vgpr1, %4,
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# CHECK: FLAT_STORE_DWORDX3 %vgpr0_vgpr1, %6,
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---
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name: main
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 1, class: sreg_32_xm0, preferred-register: '%1' }
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- { id: 2, class: vreg_64, preferred-register: '%2' }
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- { id: 3, class: vreg_64 }
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- { id: 4, class: vreg_64 }
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- { id: 5, class: vreg_64 }
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- { id: 6, class: vreg_96 }
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- { id: 7, class: vreg_96 }
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- { id: 8, class: vreg_128 }
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- { id: 9, class: vreg_128 }
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liveins:
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- { reg: '%sgpr6', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0.entry:
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liveins: %sgpr0, %vgpr0_vgpr1
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%3 = IMPLICIT_DEF
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undef %4.sub0 = COPY %sgpr0
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%4.sub1 = COPY %3.sub0
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undef %5.sub0 = COPY %4.sub1
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%5.sub1 = COPY %4.sub0
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FLAT_STORE_DWORDX2 %vgpr0_vgpr1, killed %5, 0, 0, 0, implicit %exec, implicit %flat_scr
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%6 = IMPLICIT_DEF
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undef %7.sub0_sub1 = COPY %6
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%7.sub2 = COPY %3.sub0
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FLAT_STORE_DWORDX3 %vgpr0_vgpr1, killed %7, 0, 0, 0, implicit %exec, implicit %flat_scr
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%8 = IMPLICIT_DEF
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undef %9.sub0_sub1_sub2 = COPY %8
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%9.sub3 = COPY %3.sub0
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FLAT_STORE_DWORDX4 %vgpr0_vgpr1, killed %9, 0, 0, 0, implicit %exec, implicit %flat_scr
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...
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