Enable a couple of xforms:

- (store (bitconvert v)) -> (store v) if resultant store does not require
higher alignment
- (bitconvert (load v)) -> (load (bitconvert*)v) if resultant load does not
require higher alignment

llvm-svn: 36908
This commit is contained in:
Evan Cheng 2007-05-07 21:27:48 +00:00
parent 9a25b3afcd
commit a4cf58a103
1 changed files with 27 additions and 16 deletions

View File

@ -34,7 +34,9 @@
#include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h" #include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetOptions.h"
#include "llvm/Support/Compiler.h" #include "llvm/Support/Compiler.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
@ -2569,10 +2571,14 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
// fold (conv (load x)) -> (load (conv*)x) // fold (conv (load x)) -> (load (conv*)x)
// FIXME: These xforms need to know that the resultant load doesn't need a // If the resultant load doesn't need a higher alignment than the original!
// higher alignment than the original! if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) { TLI.isOperationLegal(ISD::LOAD, VT)) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0); LoadSDNode *LN0 = cast<LoadSDNode>(N0);
unsigned Align = TLI.getTargetMachine().getTargetData()->
getPrefTypeAlignment(getTypeForValueType(VT));
unsigned OrigAlign = LN0->getAlignment();
if (Align <= OrigAlign) {
SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
LN0->getSrcValue(), LN0->getSrcValueOffset(), LN0->getSrcValue(), LN0->getSrcValueOffset(),
LN0->isVolatile(), LN0->getAlignment()); LN0->isVolatile(), LN0->getAlignment());
@ -2581,6 +2587,7 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
Load.getValue(1)); Load.getValue(1));
return Load; return Load;
} }
}
return SDOperand(); return SDOperand();
} }
@ -3414,10 +3421,14 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) {
SDOperand Value = ST->getValue(); SDOperand Value = ST->getValue();
SDOperand Ptr = ST->getBasePtr(); SDOperand Ptr = ST->getBasePtr();
// If this is a store of a bit convert, store the input value. // If this is a store of a bit convert, store the input value if the
// FIXME: This needs to know that the resultant store does not need a // resultant store does not need a higher alignment than the original.
// higher alignment than the original. if (Value.getOpcode() == ISD::BIT_CONVERT) {
if (0 && Value.getOpcode() == ISD::BIT_CONVERT) { unsigned Align = ST->getAlignment();
MVT::ValueType SVT = Value.getOperand(0).getValueType();
unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
getPrefTypeAlignment(getTypeForValueType(SVT));
if (Align <= OrigAlign)
return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
ST->getSrcValueOffset()); ST->getSrcValueOffset());
} }