Compile varargs functions for SPARCv9.
With a little help from the frontend, it looks like the standard va_* intrinsics can do the job. Also clean up an old bitcast hack in LowerVAARG that dealt with unaligned double loads. Load SDNodes can specify an alignment now. Still missing: Calling varargs functions with float arguments. llvm-svn: 179961
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@ -543,6 +543,9 @@ LowerFormalArguments_64(SDValue Chain,
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getTargetMachine(), ArgLocs, *DAG.getContext());
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getTargetMachine(), ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
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CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
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// The argument array begins at %fp+BIAS+128, after the register save area.
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const unsigned ArgArea = 128;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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CCValAssign &VA = ArgLocs[i];
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if (VA.isRegLoc()) {
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if (VA.isRegLoc()) {
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@ -586,7 +589,7 @@ LowerFormalArguments_64(SDValue Chain,
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assert(VA.isMemLoc());
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assert(VA.isMemLoc());
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// The CC_Sparc64_Full/Half functions compute stack offsets relative to the
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// The CC_Sparc64_Full/Half functions compute stack offsets relative to the
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// beginning of the arguments area at %fp+BIAS+128.
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// beginning of the arguments area at %fp+BIAS+128.
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unsigned Offset = VA.getLocMemOffset() + 128;
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unsigned Offset = VA.getLocMemOffset() + ArgArea;
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unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
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unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
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// Adjust offset for extended arguments, SPARC is big-endian.
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// Adjust offset for extended arguments, SPARC is big-endian.
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// The caller will have written the full slot with extended bytes, but we
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// The caller will have written the full slot with extended bytes, but we
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@ -599,6 +602,41 @@ LowerFormalArguments_64(SDValue Chain,
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MachinePointerInfo::getFixedStack(FI),
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MachinePointerInfo::getFixedStack(FI),
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false, false, false, 0));
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false, false, false, 0));
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}
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}
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if (!IsVarArg)
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return Chain;
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// This function takes variable arguments, some of which may have been passed
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// in registers %i0-%i5. Variable floating point arguments are never passed
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// in floating point registers. They go on %i0-%i5 or on the stack like
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// integer arguments.
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//
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// The va_start intrinsic needs to know the offset to the first variable
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// argument.
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unsigned ArgOffset = CCInfo.getNextStackOffset();
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SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
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// Skip the 128 bytes of register save area.
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FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
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Subtarget->getStackPointerBias());
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// Save the variable arguments that were passed in registers.
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// The caller is required to reserve stack space for 6 arguments regardless
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// of how many arguments were actually passed.
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SmallVector<SDValue, 8> OutChains;
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for (; ArgOffset < 6*8; ArgOffset += 8) {
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unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
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SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
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int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true);
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OutChains.push_back(DAG.getStore(Chain, DL, VArg,
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DAG.getFrameIndex(FI, getPointerTy()),
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MachinePointerInfo::getFixedStack(FI),
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false, false, 0));
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}
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if (!OutChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
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&OutChains[0], OutChains.size());
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return Chain;
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return Chain;
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}
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}
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@ -1524,14 +1562,13 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
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// vastart just stores the address of the VarArgsFrameIndex slot into the
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// vastart just stores the address of the VarArgsFrameIndex slot into the
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// memory location argument.
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// memory location argument.
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DebugLoc dl = Op.getDebugLoc();
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DebugLoc DL = Op.getDebugLoc();
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SDValue Offset =
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SDValue Offset =
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DAG.getNode(ISD::ADD, dl, MVT::i32,
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DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(),
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DAG.getRegister(SP::I6, MVT::i32),
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DAG.getRegister(SP::I6, TLI.getPointerTy()),
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DAG.getConstant(FuncInfo->getVarArgsFrameOffset(),
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DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset()));
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MVT::i32));
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const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
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const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
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return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1),
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return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
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MachinePointerInfo(SV), false, false, 0);
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MachinePointerInfo(SV), false, false, 0);
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}
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}
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@ -1540,33 +1577,22 @@ static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
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EVT VT = Node->getValueType(0);
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EVT VT = Node->getValueType(0);
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SDValue InChain = Node->getOperand(0);
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SDValue InChain = Node->getOperand(0);
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SDValue VAListPtr = Node->getOperand(1);
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SDValue VAListPtr = Node->getOperand(1);
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EVT PtrVT = VAListPtr.getValueType();
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const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
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const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
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DebugLoc dl = Node->getDebugLoc();
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DebugLoc DL = Node->getDebugLoc();
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SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr,
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SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr,
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MachinePointerInfo(SV), false, false, false, 0);
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MachinePointerInfo(SV), false, false, false, 0);
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// Increment the pointer, VAList, to the next vaarg
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// Increment the pointer, VAList, to the next vaarg.
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SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
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SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
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DAG.getConstant(VT.getSizeInBits()/8,
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DAG.getIntPtrConstant(VT.getSizeInBits()/8));
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MVT::i32));
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// Store the incremented VAList to the legalized pointer.
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// Store the incremented VAList to the legalized pointer
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InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
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InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
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VAListPtr, MachinePointerInfo(SV), false, false, 0);
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VAListPtr, MachinePointerInfo(SV), false, false, 0);
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// Load the actual argument out of the pointer VAList, unless this is an
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// Load the actual argument out of the pointer VAList.
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// f64 load.
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// We can't count on greater alignment than the word size.
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if (VT != MVT::f64)
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return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
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return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(),
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false, false, false,
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false, false, false, 0);
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std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
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// Otherwise, load it as i64, then do a bitconvert.
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SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, MachinePointerInfo(),
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false, false, false, 0);
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// Bit-Convert the value to f64.
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SDValue Ops[2] = {
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DAG.getNode(ISD::BITCAST, dl, MVT::f64, V),
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V.getValue(1)
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};
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return DAG.getMergeValues(Ops, 2, dl);
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}
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}
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static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
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static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
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@ -0,0 +1,62 @@
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; RUN: llc < %s -disable-block-placement | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128"
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target triple = "sparcv9-sun-solaris"
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; CHECK: varargsfunc
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; 128 byte save ares + 1 alloca rounded up to 16 bytes alignment.
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; CHECK: save %sp, -144, %sp
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; Store the ... arguments to the argument array. The order is not important.
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; CHECK: stx %i5, [%fp+2215]
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; CHECK: stx %i4, [%fp+2207]
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; CHECK: stx %i3, [%fp+2199]
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; CHECK: stx %i2, [%fp+2191]
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; Store the address of the ... args to %ap at %fp+BIAS+128-8
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; add %fp, 2191, [[R:[gilo][0-7]]]
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; stx [[R]], [%fp+2039]
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define double @varargsfunc(i8* nocapture %fmt, double %sum, ...) {
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entry:
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%ap = alloca i8*, align 4
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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br label %for.cond
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for.cond:
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%fmt.addr.0 = phi i8* [ %fmt, %entry ], [ %incdec.ptr, %for.cond.backedge ]
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%sum.addr.0 = phi double [ %sum, %entry ], [ %sum.addr.0.be, %for.cond.backedge ]
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%incdec.ptr = getelementptr inbounds i8* %fmt.addr.0, i64 1
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%0 = load i8* %fmt.addr.0, align 1
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%conv = sext i8 %0 to i32
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switch i32 %conv, label %sw.default [
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i32 105, label %sw.bb
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i32 102, label %sw.bb3
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]
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; CHECK: sw.bb
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; ldx [%fp+2039], %[[AP:[gilo][0-7]]]
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; add %[[AP]], 4, %[[AP2:[gilo][0-7]]]
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; stx %[[AP2]], [%fp+2039]
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; ld [%[[AP]]]
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sw.bb:
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%1 = va_arg i8** %ap, i32
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%conv2 = sitofp i32 %1 to double
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br label %for.cond.backedge
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; CHECK: sw.bb3
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; ldx [%fp+2039], %[[AP:[gilo][0-7]]]
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; add %[[AP]], 8, %[[AP2:[gilo][0-7]]]
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; stx %[[AP2]], [%fp+2039]
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; ldd [%[[AP]]]
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sw.bb3:
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%2 = va_arg i8** %ap, double
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br label %for.cond.backedge
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for.cond.backedge:
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%.pn = phi double [ %2, %sw.bb3 ], [ %conv2, %sw.bb ]
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%sum.addr.0.be = fadd double %.pn, %sum.addr.0
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br label %for.cond
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sw.default:
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ret double %sum.addr.0
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}
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declare void @llvm.va_start(i8*)
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