replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Compile varargs functions for SPARCv9. 

With a little help from the frontend, it looks like the standard va_*
intrinsics can do the job.

Also clean up an old bitcast hack in LowerVAARG that dealt with
unaligned double loads. Load SDNodes can specify an alignment now.

Still missing: Calling varargs functions with float arguments.

llvm-svn: 179961
This commit is contained in:
Jakob Stoklund Olesen 2013-04-20 22:49:16 +00:00
parent 8aca44a623
commit a41f91ea8e
2 changed files with 119 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

88
llvm/lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -543,6 +543,9 @@ LowerFormalArguments_64(SDValue Chain,
getTargetMachine(), ArgLocs, *DAG.getContext());
CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
// The argument array begins at %fp+BIAS+128, after the register save area.
const unsigned ArgArea = 128;
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
if (VA.isRegLoc()) {
@ -586,7 +589,7 @@ LowerFormalArguments_64(SDValue Chain,
assert(VA.isMemLoc());
// The CC_Sparc64_Full/Half functions compute stack offsets relative to the
// beginning of the arguments area at %fp+BIAS+128.
unsigned Offset = VA.getLocMemOffset() + 128;
unsigned Offset = VA.getLocMemOffset() + ArgArea;
unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
// Adjust offset for extended arguments, SPARC is big-endian.
// The caller will have written the full slot with extended bytes, but we
@ -599,6 +602,41 @@ LowerFormalArguments_64(SDValue Chain,
MachinePointerInfo::getFixedStack(FI),
false, false, false, 0));
}
if (!IsVarArg)
return Chain;
// This function takes variable arguments, some of which may have been passed
// in registers %i0-%i5. Variable floating point arguments are never passed
// in floating point registers. They go on %i0-%i5 or on the stack like
// integer arguments.
//
// The va_start intrinsic needs to know the offset to the first variable
// argument.
unsigned ArgOffset = CCInfo.getNextStackOffset();
SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
// Skip the 128 bytes of register save area.
FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
Subtarget->getStackPointerBias());
// Save the variable arguments that were passed in registers.
// The caller is required to reserve stack space for 6 arguments regardless
// of how many arguments were actually passed.
SmallVector<SDValue, 8> OutChains;
for (; ArgOffset < 6*8; ArgOffset += 8) {
unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true);
OutChains.push_back(DAG.getStore(Chain, DL, VArg,
DAG.getFrameIndex(FI, getPointerTy()),
MachinePointerInfo::getFixedStack(FI),
false, false, 0));
}
if (!OutChains.empty())
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
&OutChains[0], OutChains.size());
return Chain;
}
@ -1524,14 +1562,13 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
DebugLoc dl = Op.getDebugLoc();
DebugLoc DL = Op.getDebugLoc();
SDValue Offset =
DAG.getNode(ISD::ADD, dl, MVT::i32,
DAG.getRegister(SP::I6, MVT::i32),
DAG.getConstant(FuncInfo->getVarArgsFrameOffset(),
MVT::i32));
DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(),
DAG.getRegister(SP::I6, TLI.getPointerTy()),
DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset()));
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1),
return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
MachinePointerInfo(SV), false, false, 0);
}
@ -1540,33 +1577,22 @@ static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
EVT VT = Node->getValueType(0);
SDValue InChain = Node->getOperand(0);
SDValue VAListPtr = Node->getOperand(1);
EVT PtrVT = VAListPtr.getValueType();
const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
DebugLoc dl = Node->getDebugLoc();
SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr,
DebugLoc DL = Node->getDebugLoc();
SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr,
MachinePointerInfo(SV), false, false, false, 0);
// Increment the pointer, VAList, to the next vaarg
SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
DAG.getConstant(VT.getSizeInBits()/8,
MVT::i32));
// Store the incremented VAList to the legalized pointer
InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
// Increment the pointer, VAList, to the next vaarg.
SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
DAG.getIntPtrConstant(VT.getSizeInBits()/8));
// Store the incremented VAList to the legalized pointer.
InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
VAListPtr, MachinePointerInfo(SV), false, false, 0);
// Load the actual argument out of the pointer VAList, unless this is an
// f64 load.
if (VT != MVT::f64)
return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(),
false, false, false, 0);
// Otherwise, load it as i64, then do a bitconvert.
SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, MachinePointerInfo(),
false, false, false, 0);
// Bit-Convert the value to f64.
SDValue Ops[2] = {
DAG.getNode(ISD::BITCAST, dl, MVT::f64, V),
V.getValue(1)
};
return DAG.getMergeValues(Ops, 2, dl);
// Load the actual argument out of the pointer VAList.
// We can't count on greater alignment than the word size.
return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
false, false, false,
std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
}
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {

62
llvm/test/CodeGen/SPARC/varargs.ll Normal file
View File

@ -0,0 +1,62 @@
; RUN: llc < %s -disable-block-placement | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128"
target triple = "sparcv9-sun-solaris"
; CHECK: varargsfunc
; 128 byte save ares + 1 alloca rounded up to 16 bytes alignment.
; CHECK: save %sp, -144, %sp
; Store the ... arguments to the argument array. The order is not important.
; CHECK: stx %i5, [%fp+2215]
; CHECK: stx %i4, [%fp+2207]
; CHECK: stx %i3, [%fp+2199]
; CHECK: stx %i2, [%fp+2191]
; Store the address of the ... args to %ap at %fp+BIAS+128-8
; add %fp, 2191, [[R:[gilo][0-7]]]
; stx [[R]], [%fp+2039]
define double @varargsfunc(i8* nocapture %fmt, double %sum, ...) {
entry:
%ap = alloca i8*, align 4
%ap1 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap1)
br label %for.cond
for.cond:
%fmt.addr.0 = phi i8* [ %fmt, %entry ], [ %incdec.ptr, %for.cond.backedge ]
%sum.addr.0 = phi double [ %sum, %entry ], [ %sum.addr.0.be, %for.cond.backedge ]
%incdec.ptr = getelementptr inbounds i8* %fmt.addr.0, i64 1
%0 = load i8* %fmt.addr.0, align 1
%conv = sext i8 %0 to i32
switch i32 %conv, label %sw.default [
i32 105, label %sw.bb
i32 102, label %sw.bb3
]
; CHECK: sw.bb
; ldx [%fp+2039], %[[AP:[gilo][0-7]]]
; add %[[AP]], 4, %[[AP2:[gilo][0-7]]]
; stx %[[AP2]], [%fp+2039]
; ld [%[[AP]]]
sw.bb:
%1 = va_arg i8** %ap, i32
%conv2 = sitofp i32 %1 to double
br label %for.cond.backedge
; CHECK: sw.bb3
; ldx [%fp+2039], %[[AP:[gilo][0-7]]]
; add %[[AP]], 8, %[[AP2:[gilo][0-7]]]
; stx %[[AP2]], [%fp+2039]
; ldd [%[[AP]]]
sw.bb3:
%2 = va_arg i8** %ap, double
br label %for.cond.backedge
for.cond.backedge:
%.pn = phi double [ %2, %sw.bb3 ], [ %conv2, %sw.bb ]
%sum.addr.0.be = fadd double %.pn, %sum.addr.0
br label %for.cond
sw.default:
ret double %sum.addr.0
}
declare void @llvm.va_start(i8*)