AMDGPU: Move hazard avoidance out of waitcnt pass.
This is mostly moving VMEM clause breaking into the hazard recognizer. Also move another hazard currently handled in the waitcnt pass. Also stops breaking clauses unless xnack is enabled. llvm-svn: 318557
This commit is contained in:
Matt Arsenault
parent
c0a81071d3
commit
a41351e37c
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@ -806,10 +806,14 @@ public:
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return getGeneration() >= AMDGPUSubtarget::GFX9;
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}
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bool hasReadM0Hazard() const {
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bool hasReadM0MovRelInterpHazard() const {
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return getGeneration() >= AMDGPUSubtarget::GFX9;
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}
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bool hasReadM0SendMsgHazard() const {
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return getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS;
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}
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unsigned getKernArgSegmentSize(const MachineFunction &MF,
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unsigned ExplictArgBytes) const;
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@ -87,6 +87,18 @@ static bool isSMovRel(unsigned Opcode) {
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}
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}
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static bool isSendMsgTraceDataOrGDS(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case AMDGPU::S_SENDMSG:
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case AMDGPU::S_SENDMSGHALT:
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case AMDGPU::S_TTRACEDATA:
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return true;
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default:
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// TODO: GDS
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return false;
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}
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}
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static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr) {
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const MachineOperand *RegOp = TII->getNamedOperand(RegInstr,
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AMDGPU::OpName::simm16);
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@ -100,7 +112,10 @@ GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
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if (SIInstrInfo::isSMRD(*MI) && checkSMRDHazards(MI) > 0)
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return NoopHazard;
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if (SIInstrInfo::isVMEM(*MI) && checkVMEMHazards(MI) > 0)
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// FIXME: Should flat be considered vmem?
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if ((SIInstrInfo::isVMEM(*MI) ||
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SIInstrInfo::isFLAT(*MI))
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&& checkVMEMHazards(MI) > 0)
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return NoopHazard;
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if (SIInstrInfo::isVALU(*MI) && checkVALUHazards(MI) > 0)
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@ -124,7 +139,12 @@ GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
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if (isRFE(MI->getOpcode()) && checkRFEHazards(MI) > 0)
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return NoopHazard;
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if ((TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode())) &&
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if (ST.hasReadM0MovRelInterpHazard() &&
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(TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode())) &&
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checkReadM0Hazards(MI) > 0)
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return NoopHazard;
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if (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(*MI) &&
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checkReadM0Hazards(MI) > 0)
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return NoopHazard;
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@ -144,26 +164,20 @@ unsigned GCNHazardRecognizer::PreEmitNoops(MachineInstr *MI) {
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if (SIInstrInfo::isSMRD(*MI))
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return std::max(WaitStates, checkSMRDHazards(MI));
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if (SIInstrInfo::isVALU(*MI)) {
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WaitStates = std::max(WaitStates, checkVALUHazards(MI));
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if (SIInstrInfo::isVALU(*MI))
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WaitStates = std::max(WaitStates, checkVALUHazards(MI));
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if (SIInstrInfo::isVMEM(*MI))
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WaitStates = std::max(WaitStates, checkVMEMHazards(MI));
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if (SIInstrInfo::isVMEM(*MI) || SIInstrInfo::isFLAT(*MI))
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WaitStates = std::max(WaitStates, checkVMEMHazards(MI));
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if (SIInstrInfo::isDPP(*MI))
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WaitStates = std::max(WaitStates, checkDPPHazards(MI));
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if (SIInstrInfo::isDPP(*MI))
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WaitStates = std::max(WaitStates, checkDPPHazards(MI));
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if (isDivFMas(MI->getOpcode()))
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WaitStates = std::max(WaitStates, checkDivFMasHazards(MI));
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if (isDivFMas(MI->getOpcode()))
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WaitStates = std::max(WaitStates, checkDivFMasHazards(MI));
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if (isRWLane(MI->getOpcode()))
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WaitStates = std::max(WaitStates, checkRWLaneHazards(MI));
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if (TII.isVINTRP(*MI))
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WaitStates = std::max(WaitStates, checkReadM0Hazards(MI));
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return WaitStates;
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}
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if (isRWLane(MI->getOpcode()))
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WaitStates = std::max(WaitStates, checkRWLaneHazards(MI));
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if (isSGetReg(MI->getOpcode()))
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return std::max(WaitStates, checkGetRegHazards(MI));
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@ -174,7 +188,11 @@ unsigned GCNHazardRecognizer::PreEmitNoops(MachineInstr *MI) {
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if (isRFE(MI->getOpcode()))
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return std::max(WaitStates, checkRFEHazards(MI));
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if (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode()))
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if (ST.hasReadM0MovRelInterpHazard() && (TII.isVINTRP(*MI) ||
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isSMovRel(MI->getOpcode())))
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return std::max(WaitStates, checkReadM0Hazards(MI));
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if (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(*MI))
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return std::max(WaitStates, checkReadM0Hazards(MI));
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return WaitStates;
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@ -282,12 +300,14 @@ void GCNHazardRecognizer::addClauseInst(const MachineInstr &MI) {
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addRegsToSet(TRI, MI.uses(), ClauseUses);
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}
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int GCNHazardRecognizer::checkSMEMSoftClauseHazards(MachineInstr *SMEM) {
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int GCNHazardRecognizer::checkSoftClauseHazards(MachineInstr *MEM) {
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// SMEM soft clause are only present on VI+, and only matter if xnack is
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// enabled.
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if (!ST.isXNACKEnabled())
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return 0;
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bool IsSMRD = TII.isSMRD(*MEM);
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resetClause();
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// A soft-clause is any group of consecutive SMEM instructions. The
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@ -303,7 +323,10 @@ int GCNHazardRecognizer::checkSMEMSoftClauseHazards(MachineInstr *SMEM) {
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for (MachineInstr *MI : EmittedInstrs) {
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// When we hit a non-SMEM instruction then we have passed the start of the
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// clause and we can stop.
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if (!MI || !SIInstrInfo::isSMRD(*MI))
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if (!MI)
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break;
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if (IsSMRD != SIInstrInfo::isSMRD(*MI))
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break;
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addClauseInst(*MI);
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@ -312,13 +335,13 @@ int GCNHazardRecognizer::checkSMEMSoftClauseHazards(MachineInstr *SMEM) {
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if (ClauseDefs.none())
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return 0;
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// FIXME: When we support stores, we need to make sure not to put loads and
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// stores in the same clause if they use the same address. For now, just
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// start a new clause whenever we see a store.
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if (SMEM->mayStore())
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// We need to make sure not to put loads and stores in the same clause if they
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// use the same address. For now, just start a new clause whenever we see a
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// store.
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if (MEM->mayStore())
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return 1;
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addClauseInst(*SMEM);
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addClauseInst(*MEM);
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// If the set of defs and uses intersect then we cannot add this instruction
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// to the clause, so we have a hazard.
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@ -329,7 +352,7 @@ int GCNHazardRecognizer::checkSMRDHazards(MachineInstr *SMRD) {
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const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
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int WaitStatesNeeded = 0;
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WaitStatesNeeded = checkSMEMSoftClauseHazards(SMRD);
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WaitStatesNeeded = checkSoftClauseHazards(SMRD);
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// This SMRD hazard only affects SI.
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if (ST.getGeneration() != SISubtarget::SOUTHERN_ISLANDS)
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@ -369,18 +392,15 @@ int GCNHazardRecognizer::checkSMRDHazards(MachineInstr *SMRD) {
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}
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int GCNHazardRecognizer::checkVMEMHazards(MachineInstr* VMEM) {
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const SIInstrInfo *TII = ST.getInstrInfo();
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if (ST.getGeneration() < SISubtarget::VOLCANIC_ISLANDS)
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return 0;
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const SIRegisterInfo &TRI = TII->getRegisterInfo();
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int WaitStatesNeeded = checkSoftClauseHazards(VMEM);
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// A read of an SGPR by a VMEM instruction requires 5 wait states when the
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// SGPR was written by a VALU Instruction.
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int VmemSgprWaitStates = 5;
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int WaitStatesNeeded = 0;
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auto IsHazardDefFn = [TII] (MachineInstr *MI) { return TII->isVALU(*MI); };
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const int VmemSgprWaitStates = 5;
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auto IsHazardDefFn = [this] (MachineInstr *MI) { return TII.isVALU(*MI); };
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for (const MachineOperand &Use : VMEM->uses()) {
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if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
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@ -598,11 +618,8 @@ int GCNHazardRecognizer::checkAnyInstHazards(MachineInstr *MI) {
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}
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int GCNHazardRecognizer::checkReadM0Hazards(MachineInstr *MI) {
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if (!ST.hasReadM0Hazard())
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return 0;
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const SIInstrInfo *TII = ST.getInstrInfo();
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int SMovRelWaitStates = 1;
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const int SMovRelWaitStates = 1;
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auto IsHazardFn = [TII] (MachineInstr *MI) {
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return TII->isSALU(*MI);
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};
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@ -58,7 +58,7 @@ class GCNHazardRecognizer final : public ScheduleHazardRecognizer {
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[](MachineInstr *) { return true; });
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int getWaitStatesSinceSetReg(function_ref<bool(MachineInstr *)> IsHazard);
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int checkSMEMSoftClauseHazards(MachineInstr *SMEM);
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int checkSoftClauseHazards(MachineInstr *SMEM);
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int checkSMRDHazards(MachineInstr *SMRD);
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int checkVMEMHazards(MachineInstr* VMEM);
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int checkDPPHazards(MachineInstr *DPP);
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@ -1522,8 +1522,6 @@ void SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF,
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ScoreBrackets->dump();
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});
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bool InsertNOP = false;
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// Walk over the instructions.
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for (MachineBasicBlock::iterator Iter = Block.begin(), E = Block.end();
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Iter != E;) {
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@ -1624,58 +1622,6 @@ void SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF,
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VCCZBugHandledSet.insert(&Inst);
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}
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if (ST->getGeneration() >= SISubtarget::VOLCANIC_ISLANDS) {
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// This avoids a s_nop after a waitcnt has just been inserted.
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if (!SWaitInst && InsertNOP) {
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BuildMI(Block, Inst, DebugLoc(), TII->get(AMDGPU::S_NOP)).addImm(0);
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}
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InsertNOP = false;
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// Any occurrence of consecutive VMEM or SMEM instructions forms a VMEM
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// or SMEM clause, respectively.
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//
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// The temporary workaround is to break the clauses with S_NOP.
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//
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// The proper solution would be to allocate registers such that all source
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// and destination registers don't overlap, e.g. this is illegal:
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// r0 = load r2
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// r2 = load r0
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bool IsSMEM = false;
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bool IsVMEM = false;
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if (TII->isSMRD(Inst))
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IsSMEM = true;
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else if (TII->usesVM_CNT(Inst))
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IsVMEM = true;
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++Iter;
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if (Iter == E)
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break;
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MachineInstr &Next = *Iter;
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// TODO: How about consecutive SMEM instructions?
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// The comments above says break the clause but the code does not.
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// if ((TII->isSMRD(next) && isSMEM) ||
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if (!IsSMEM && TII->usesVM_CNT(Next) && IsVMEM &&
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// TODO: Enable this check when hasSoftClause is upstreamed.
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// ST->hasSoftClauses() &&
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ST->isXNACKEnabled()) {
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// Insert a NOP to break the clause.
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InsertNOP = true;
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continue;
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}
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// There must be "S_NOP 0" between an instruction writing M0 and
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// S_SENDMSG.
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if ((Next.getOpcode() == AMDGPU::S_SENDMSG ||
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Next.getOpcode() == AMDGPU::S_SENDMSGHALT) &&
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Inst.definesRegister(AMDGPU::M0))
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InsertNOP = true;
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continue;
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}
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++Iter;
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}
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@ -0,0 +1,580 @@
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# RUN: llc -march=amdgcn -mcpu=carrizo -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK %s
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# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK %s
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---
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# Trivial clause at beginning of program
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name: trivial_clause_load_flat4_x1
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body: |
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bb.0:
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; GCN-LABEL: name: trivial_clause_load_flat4_x1
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; GCN: %vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
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; GCN-NEXT: S_ENDPGM
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%vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
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S_ENDPGM
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...
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---
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# Trivial clause at beginning of program
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name: trivial_clause_load_flat4_x2
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body: |
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bb.0:
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; GCN-LABEL: name: trivial_clause_load_flat4_x2
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; GCN: %vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
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; GCN-NEXT: %vgpr1 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
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; GCN-NEXT: S_ENDPGM
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%vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
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%vgpr1 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
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S_ENDPGM
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...
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---
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# Trivial clause at beginning of program
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name: trivial_clause_load_flat4_x3
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body: |
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bb.0:
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; GCN-LABEL: name: trivial_clause_load_flat4_x3
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; GCN: %vgpr0 = FLAT_LOAD_DWORD %vgpr3_vgpr4, 0, 0, 0, implicit %exec, implicit %flat_scr
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; GCN-NEXT: %vgpr1 = FLAT_LOAD_DWORD %vgpr5_vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr
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; GCN-NEXT: %vgpr2 = FLAT_LOAD_DWORD %vgpr7_vgpr8, 0, 0, 0, implicit %exec, implicit %flat_scr
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; GCN-NEXT: S_ENDPGM
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%vgpr0 = FLAT_LOAD_DWORD %vgpr3_vgpr4, 0, 0, 0, implicit %exec, implicit %flat_scr
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%vgpr1 = FLAT_LOAD_DWORD %vgpr5_vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr
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%vgpr2 = FLAT_LOAD_DWORD %vgpr7_vgpr8, 0, 0, 0, implicit %exec, implicit %flat_scr
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S_ENDPGM
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...
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---
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# Trivial clause at beginning of program
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name: trivial_clause_load_flat4_x4
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body: |
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bb.0:
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; GCN-LABEL: name: trivial_clause_load_flat4_x4
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; GCN: %vgpr0 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
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; GCN-NEXT: %vgpr1 = FLAT_LOAD_DWORD %vgpr6_vgpr7, 0, 0, 0, implicit %exec, implicit %flat_scr
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; GCN-NEXT: %vgpr2 = FLAT_LOAD_DWORD %vgpr8_vgpr9, 0, 0, 0, implicit %exec, implicit %flat_scr
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; GCN-NEXT: %vgpr3 = FLAT_LOAD_DWORD %vgpr10_vgpr11, 0, 0, 0, implicit %exec, implicit %flat_scr
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; GCN-NEXT: S_ENDPGM
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%vgpr0 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
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%vgpr1 = FLAT_LOAD_DWORD %vgpr6_vgpr7, 0, 0, 0, implicit %exec, implicit %flat_scr
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%vgpr2 = FLAT_LOAD_DWORD %vgpr8_vgpr9, 0, 0, 0, implicit %exec, implicit %flat_scr
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%vgpr3 = FLAT_LOAD_DWORD %vgpr10_vgpr11, 0, 0, 0, implicit %exec, implicit %flat_scr
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S_ENDPGM
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...
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---
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# Reuse of same input pointer is OK
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name: trivial_clause_load_flat4_x2_sameptr
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body: |
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bb.0:
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; GCN-LABEL: name: trivial_clause_load_flat4_x2_sameptr
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; GCN: %vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
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; GCN-NEXT: %vgpr1 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
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; GCN-NEXT: S_ENDPGM
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%vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
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%vgpr1 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
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S_ENDPGM
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...
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---
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# 32-bit load partially clobbers its own ptr reg
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name: flat_load4_overwrite_ptr_lo
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body: |
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bb.0:
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; GCN-LABEL: name: flat_load4_overwrite_ptr_lo
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; GCN: %vgpr0 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
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; GCN-NEXT: S_ENDPGM
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%vgpr0 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
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S_ENDPGM
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...
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---
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# 32-bit load partially clobbers its own ptr reg
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name: flat_load4_overwrite_ptr_hi
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body: |
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bb.0:
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; GCN-LABEL: name: flat_load4_overwrite_ptr_hi
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; GCN: %vgpr1 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr1 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
# 64-bit load clobbers its own ptr reg
|
||||
name: flat_load8_overwrite_ptr
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: flat_load8_overwrite_ptr
|
||||
; GCN: %vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
# vmcnt has 4 bits, so maximum 16 outstanding loads. The waitcnt
|
||||
# breaks the clause.
|
||||
|
||||
|
||||
name: break_clause_at_max_clause_size_flat_load4
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: break_clause_at_max_clause_size_flat_load4
|
||||
; GCN: %vgpr2 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr3 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr4 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr5 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr6 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr7 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr8 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr9 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr10 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr11 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr12 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr13 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr14 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr15 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr16 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr17 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: %vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %sgpr0 = S_MOV_B32 %sgpr0, implicit %vgpr2, implicit %vgpr3, implicit %vgpr4, implicit %vgpr5, implicit %vgpr6, implicit %vgpr7, implicit %vgpr8, implicit %vgpr9, implicit %vgpr10, implicit %vgpr11, implicit %vgpr12, implicit %vgpr13, implicit %vgpr14, implicit %vgpr15, implicit %vgpr16, implicit %vgpr17, implicit %vgpr18
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr2 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr3 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr4 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr5 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
|
||||
%vgpr6 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr7 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr8 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr9 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
|
||||
%vgpr10 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr11 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr12 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr13 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
|
||||
%vgpr14 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr15 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr16 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr17 = FLAT_LOAD_DWORD %vgpr0_vgpr1, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%sgpr0 = S_MOV_B32 %sgpr0, implicit %vgpr2, implicit %vgpr3, implicit %vgpr4, implicit %vgpr5, implicit %vgpr6, implicit %vgpr7, implicit %vgpr8, implicit %vgpr9, implicit %vgpr10, implicit %vgpr11, implicit %vgpr12, implicit %vgpr13, implicit %vgpr14, implicit %vgpr15, implicit %vgpr16, implicit %vgpr17, implicit %vgpr18
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
|
||||
name: break_clause_simple_load_flat4_lo_ptr
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: break_clause_simple_load_flat4_lo_ptr
|
||||
; GCN: %vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: %vgpr2 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr2 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
|
||||
name: break_clause_simple_load_flat4_hi_ptr
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: break_clause_simple_load_flat4_hi_ptr
|
||||
; GCN: %vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: %vgpr3 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr3 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
|
||||
name: break_clause_simple_load_flat8_ptr
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: break_clause_simple_load_flat8_ptr
|
||||
; GCN: %vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: %vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
|
||||
|
||||
name: break_clause_simple_load_flat16_ptr
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: break_clause_simple_load_flat16_ptr
|
||||
; GCN: %vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: %vgpr2_vgpr3_vgpr4_vgpr5 = FLAT_LOAD_DWORDX4 %vgpr6_vgpr7, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
%vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr2_vgpr3_vgpr4_vgpr5 = FLAT_LOAD_DWORDX4 %vgpr6_vgpr7, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
|
||||
# The clause is broken by the waitcnt inserted at the end of the
|
||||
# block, so no nop is needed.
|
||||
|
||||
|
||||
name: break_clause_block_boundary_load_flat8_ptr
|
||||
|
||||
body: |
|
||||
; GCN-LABEL: name: break_clause_block_boundary_load_flat8_ptr
|
||||
; GCN: bb.0:
|
||||
; GCN-NEXT: successors: %bb.1(0x80000000)
|
||||
; GCN: %vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN: bb.1:
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: %vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
bb.0:
|
||||
%vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
|
||||
bb.1:
|
||||
%vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
# The load clobbers the pointer of the store, so it needs to break.
|
||||
|
||||
name: break_clause_store_load_into_ptr_flat4
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: break_clause_store_load_into_ptr_flat4
|
||||
; GCN: FLAT_STORE_DWORD %vgpr2_vgpr3, %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr2 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
FLAT_STORE_DWORD %vgpr2_vgpr3, %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr2 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
# The load clobbers the data of the store, so it needs to break.
|
||||
# FIXME: Would it be better to s_nop and wait later?
|
||||
|
||||
name: break_clause_store_load_into_data_flat4
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: break_clause_store_load_into_data_flat4
|
||||
; GCN: FLAT_STORE_DWORD %vgpr2_vgpr3, %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr0 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
FLAT_STORE_DWORD %vgpr2_vgpr3, %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
# Regular VALU instruction breaks clause, no nop needed
|
||||
|
||||
name: valu_inst_breaks_clause
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: valu_inst_breaks_clause
|
||||
; GCN: %vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr8 = V_MOV_B32_e32 0, implicit %exec
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: %vgpr2 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr8 = V_MOV_B32_e32 0, implicit %exec
|
||||
%vgpr2 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
# Regular SALU instruction breaks clause, no nop needed
|
||||
|
||||
name: salu_inst_breaks_clause
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: salu_inst_breaks_clause
|
||||
; GCN: %vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %sgpr8 = S_MOV_B32 0
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: %vgpr2 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%sgpr8 = S_MOV_B32 0
|
||||
%vgpr2 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
|
||||
name: ds_inst_breaks_clause
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: ds_inst_breaks_clause
|
||||
; GCN: %vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr8 = DS_READ_B32 %vgpr9, 0, 0, implicit %m0, implicit %exec
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: %vgpr2 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr8 = DS_READ_B32 %vgpr9, 0, 0, implicit %m0, implicit %exec
|
||||
%vgpr2 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
|
||||
name: smrd_inst_breaks_clause
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: smrd_inst_breaks_clause
|
||||
; GCN: %vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %sgpr8 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 0, 0
|
||||
; GCN-NEXT: %vgpr2 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%sgpr8 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 0, 0
|
||||
%vgpr2 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
# FIXME: Should this be handled?
|
||||
name: implicit_use_breaks_clause
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: implicit_use_breaks_clause
|
||||
; GCN: %vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr, implicit %vgpr4_vgpr5
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: %vgpr4_vgpr5 = FLAT_LOAD_DWORDX2 %vgpr6_vgpr7, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr, implicit %vgpr4_vgpr5
|
||||
%vgpr4_vgpr5 = FLAT_LOAD_DWORDX2 %vgpr6_vgpr7, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
name: trivial_clause_load_mubuf4_x2
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: trivial_clause_load_mubuf4_x2
|
||||
; GCN: %vgpr1 = BUFFER_LOAD_DWORD_OFFEN %vgpr2, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
; GCN-NEXT: %vgpr3 = BUFFER_LOAD_DWORD_OFFEN %vgpr4, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr1 = BUFFER_LOAD_DWORD_OFFEN %vgpr2, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
%vgpr3 = BUFFER_LOAD_DWORD_OFFEN %vgpr4, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
name: break_clause_simple_load_mubuf_offen_ptr
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: break_clause_simple_load_mubuf_offen_ptr
|
||||
; GCN: %vgpr1 = BUFFER_LOAD_DWORD_OFFEN %vgpr2, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: %vgpr2 = BUFFER_LOAD_DWORD_OFFEN %vgpr3, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr1 = BUFFER_LOAD_DWORD_OFFEN %vgpr2, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
%vgpr2 = BUFFER_LOAD_DWORD_OFFEN %vgpr3, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
# BUFFER instructions overwriting their own inputs is supposedly OK.
|
||||
|
||||
name: mubuf_load4_overwrite_ptr
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: mubuf_load4_overwrite_ptr
|
||||
; GCN: %vgpr0 = BUFFER_LOAD_DWORD_OFFEN %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
; GCN-NEXT: %vgpr1 = V_MOV_B32_e32 0, implicit %exec
|
||||
; GCN-NEXT: %vgpr2 = V_MOV_B32_e32 %vgpr0, implicit %exec
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
%vgpr0 = BUFFER_LOAD_DWORD_OFFEN %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
%vgpr1 = V_MOV_B32_e32 0, implicit %exec
|
||||
%vgpr2 = V_MOV_B32_e32 %vgpr0, implicit %exec
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
# Break a clause from interference between mubuf and flat instructions
|
||||
|
||||
name: break_clause_flat_load_mubuf_load
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: break_clause_flat_load_mubuf_load
|
||||
; GCN: %vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: %vgpr2 = BUFFER_LOAD_DWORD_OFFEN %vgpr1, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr2 = BUFFER_LOAD_DWORD_OFFEN %vgpr1, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
S_ENDPGM
|
||||
...
|
||||
# Break a clause from interference between mubuf and flat instructions
|
||||
|
||||
# GCN-LABEL: name: break_clause_mubuf_load_flat_load
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: %vgpr0 = BUFFER_LOAD_DWORD_OFFEN %vgpr1, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4
|
||||
# XNACK-NEXT: S_NOP 0
|
||||
# GCN-NEXT: %vgpr1 = FLAT_LOAD_DWORD %vgpr2_vgpr3
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
name: break_clause_mubuf_load_flat_load
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
%vgpr0 = BUFFER_LOAD_DWORD_OFFEN %vgpr1, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
%vgpr1 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
|
||||
name: break_clause_atomic_rtn_into_ptr_flat4
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: break_clause_atomic_rtn_into_ptr_flat4
|
||||
; GCN: %vgpr2 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: %vgpr4 = FLAT_ATOMIC_ADD_RTN %vgpr5_vgpr6, %vgpr7, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr2 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr4 = FLAT_ATOMIC_ADD_RTN %vgpr5_vgpr6, %vgpr7, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
name: break_clause_atomic_nortn_ptr_load_flat4
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: break_clause_atomic_nortn_ptr_load_flat4
|
||||
; GCN: FLAT_ATOMIC_ADD %vgpr0_vgpr1, %vgpr2, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr2 = FLAT_LOAD_DWORD %vgpr3_vgpr4, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
FLAT_ATOMIC_ADD %vgpr0_vgpr1, %vgpr2, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr2 = FLAT_LOAD_DWORD %vgpr3_vgpr4, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
|
||||
name: break_clause_atomic_rtn_into_ptr_mubuf4
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: break_clause_atomic_rtn_into_ptr_mubuf4
|
||||
; GCN: %vgpr1 = BUFFER_LOAD_DWORD_OFFEN %vgpr2, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: %vgpr2 = BUFFER_ATOMIC_ADD_OFFEN_RTN %vgpr2, %vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, implicit %exec
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
%vgpr1 = BUFFER_LOAD_DWORD_OFFEN %vgpr2, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
%vgpr2 = BUFFER_ATOMIC_ADD_OFFEN_RTN %vgpr2, %vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, implicit %exec
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
|
||||
name: break_clause_atomic_nortn_ptr_load_mubuf4
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: break_clause_atomic_nortn_ptr_load_mubuf4
|
||||
; GCN: BUFFER_ATOMIC_ADD_OFFEN %vgpr0, %vgpr1, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, implicit %exec
|
||||
; GCN-NEXT: %vgpr1 = BUFFER_LOAD_DWORD_OFFEN %vgpr2, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
|
||||
BUFFER_ATOMIC_ADD_OFFEN %vgpr0, %vgpr1, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, implicit %exec
|
||||
%vgpr1 = BUFFER_LOAD_DWORD_OFFEN %vgpr2, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
# Make sure there is no assert on mubuf instructions which do not have
|
||||
# vaddr, and don't add register to track.
|
||||
name: no_break_clause_mubuf_load_novaddr
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: no_break_clause_mubuf_load_novaddr
|
||||
; GCN: %vgpr1 = BUFFER_LOAD_DWORD_OFFSET %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
; GCN-NEXT: %vgpr3 = BUFFER_LOAD_DWORD_OFFSET %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
; GCN-NEXT: S_ENDPGM
|
||||
%vgpr1 = BUFFER_LOAD_DWORD_OFFSET %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
%vgpr3 = BUFFER_LOAD_DWORD_OFFSET %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
# Loads and stores using different addresses theoretically does not
|
||||
# need a nop
|
||||
name: mix_load_store_clause
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: mix_load_store_clause
|
||||
; GCN: FLAT_STORE_DWORD %vgpr0_vgpr1, %vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr10 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: FLAT_STORE_DWORD %vgpr2_vgpr3, %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr11 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
|
||||
FLAT_STORE_DWORD %vgpr0_vgpr1, %vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr10 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
FLAT_STORE_DWORD %vgpr2_vgpr3, %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr11 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
# Loads and stores using the same address needs a nop.
|
||||
|
||||
name: mix_load_store_clause_same_address
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: mix_load_store_clause_same_address
|
||||
; GCN: FLAT_STORE_DWORD %vgpr0_vgpr1, %vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr10 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; XNACK-NEXT: S_NOP 0
|
||||
; GCN-NEXT: FLAT_STORE_DWORD %vgpr0_vgpr1, %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
; GCN-NEXT: %vgpr11 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
|
||||
FLAT_STORE_DWORD %vgpr0_vgpr1, %vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr10 = FLAT_LOAD_DWORD %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
FLAT_STORE_DWORD %vgpr0_vgpr1, %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr11 = FLAT_LOAD_DWORD %vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
|
|
@ -437,22 +437,22 @@ body: |
|
|||
|
||||
# GCN-LABEL: bb.0:
|
||||
# GCN: S_MOV_B32
|
||||
# GFX9: S_NOP
|
||||
# GFX9-NEXT: S_NOP
|
||||
# GCN-NEXT: V_INTERP_P1_F32
|
||||
|
||||
# GCN-LABEL: bb.1:
|
||||
# GCN: S_MOV_B32
|
||||
# GFX9: S_NOP
|
||||
# GFX9-NEXT: S_NOP
|
||||
# GCN-NEXT: V_INTERP_P2_F32
|
||||
|
||||
# GCN-LABEL: bb.2:
|
||||
# GCN: S_MOV_B32
|
||||
# GFX9: S_NOP
|
||||
# GFX9-NEXT: S_NOP
|
||||
# GCN-NEXT: V_INTERP_P1_F32_16bank
|
||||
|
||||
# GCN-LABEL: bb.3:
|
||||
# GCN: S_MOV_B32
|
||||
# GFX9: S_NOP
|
||||
# GFX9-NEXT: S_NOP
|
||||
# GCN-NEXT: V_INTERP_MOV_F32
|
||||
|
||||
name: v_interp
|
||||
|
|
|
|||
|
|
@ -0,0 +1,49 @@
|
|||
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,GFX9 %s
|
||||
# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,VI %s
|
||||
# RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,CI %s
|
||||
# RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,SI %s
|
||||
|
||||
---
|
||||
name: m0_sendmsg
|
||||
body: |
|
||||
; GCN-LABEL: name: m0_sendmsg
|
||||
; GCN: %m0 = S_MOV_B32 -1
|
||||
; VI-NEXT: S_NOP 0
|
||||
; GFX9-NEXT: S_NOP 0
|
||||
; GCN-NEXT: S_SENDMSG 3, implicit %exec, implicit %m0
|
||||
|
||||
bb.0:
|
||||
%m0 = S_MOV_B32 -1
|
||||
S_SENDMSG 3, implicit %exec, implicit %m0
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
|
||||
name: m0_sendmsghalt
|
||||
body: |
|
||||
; GCN-LABEL: name: m0_sendmsghalt
|
||||
; GCN: %m0 = S_MOV_B32 -1
|
||||
; VI-NEXT: S_NOP 0
|
||||
; GFX9-NEXT: S_NOP 0
|
||||
; GCN-NEXT: S_SENDMSGHALT 3, implicit %exec, implicit %m0
|
||||
|
||||
bb.0:
|
||||
%m0 = S_MOV_B32 -1
|
||||
S_SENDMSGHALT 3, implicit %exec, implicit %m0
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
|
||||
name: m0_ttracedata
|
||||
body: |
|
||||
; GCN-LABEL: name: m0_ttracedata
|
||||
; GCN: %m0 = S_MOV_B32 -1
|
||||
; VI-NEXT: S_NOP 0
|
||||
; GFX9-NEXT: S_NOP 0
|
||||
; GCN-NEXT: S_TTRACEDATA implicit %m0
|
||||
|
||||
bb.0:
|
||||
%m0 = S_MOV_B32 -1
|
||||
S_TTRACEDATA implicit %m0
|
||||
S_ENDPGM
|
||||
...
|
||||
Loading…
Reference in New Issue