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A semi-gross fix for a debug info issue. When inserting the "function start" label (i.e. first label in the entry block) take care to insert it at the beginning of the block. 

llvm-svn: 46568
This commit is contained in:
Evan Cheng 2008-01-30 19:35:32 +00:00
parent 540d03bda9
commit a3ff8e6110
2 changed files with 28 additions and 9 deletions
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2
llvm/include/llvm/CodeGen/ScheduleDAG.h
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@ -24,6 +24,7 @@ namespace llvm {
struct InstrStage; struct InstrStage;
struct SUnit; struct SUnit;
class MachineConstantPool; class MachineConstantPool;
class MachineFunction;
class MachineModuleInfo; class MachineModuleInfo;
class MachineRegisterInfo; class MachineRegisterInfo;
class MachineInstr; class MachineInstr;
@ -243,6 +244,7 @@ namespace llvm {
const TargetMachine &TM; // Target processor const TargetMachine &TM; // Target processor
const TargetInstrInfo *TII; // Target instruction information const TargetInstrInfo *TII; // Target instruction information
const MRegisterInfo *MRI; // Target processor register info const MRegisterInfo *MRI; // Target processor register info
MachineFunction *MF; // Machine function
MachineRegisterInfo &RegInfo; // Virtual/real register map MachineRegisterInfo &RegInfo; // Virtual/real register map
MachineConstantPool *ConstPool; // Target constant pool MachineConstantPool *ConstPool; // Target constant pool
std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s

35
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -31,6 +31,7 @@ ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
const TargetMachine &tm) const TargetMachine &tm)
: DAG(dag), BB(bb), TM(tm), RegInfo(BB->getParent()->getRegInfo()) { : DAG(dag), BB(bb), TM(tm), RegInfo(BB->getParent()->getRegInfo()) {
TII = TM.getInstrInfo(); TII = TM.getInstrInfo();
MF = &DAG.getMachineFunction();
MRI = TM.getRegisterInfo(); MRI = TM.getRegisterInfo();
ConstPool = BB->getParent()->getConstantPool(); ConstPool = BB->getParent()->getConstantPool();
} }
@ -710,13 +711,30 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
} }
// Now that we have emitted all operands, emit this instruction itself. // Now that we have emitted all operands, emit this instruction itself.
if (!II.usesCustomDAGSchedInsertionHook()) { if (Opc == TargetInstrInfo::LABEL &&
BB->insert(BB->end(), MI); !BB->empty() && &MF->front() == BB) {
} else { // If we are inserting a LABEL and this happens to be the first label in
// Insert this instruction into the end of the basic block, potentially // the entry block, it is the "function start" label. Make sure there are
// taking some custom action. // no other instructions before it.
bool SeenLabel = false;
MachineBasicBlock::iterator MBBI = BB->begin();
while (MBBI != BB->end()) {
if (MBBI->getOpcode() == TargetInstrInfo::LABEL) {
SeenLabel = true;
break;
}
++MBBI;
}
if (!SeenLabel)
BB->insert(BB->begin(), MI);
else
BB->push_back(MI);
} else if (II.usesCustomDAGSchedInsertionHook())
// Insert this instruction into the basic block using a target
// specific inserter which may returns a new basic block.
BB = DAG.getTargetLoweringInfo().EmitInstrWithCustomInserter(MI, BB); BB = DAG.getTargetLoweringInfo().EmitInstrWithCustomInserter(MI, BB);
} else
BB->push_back(MI);
// Additional results must be an physical register def. // Additional results must be an physical register def.
if (HasPhysRegOuts) { if (HasPhysRegOuts) {
@ -870,13 +888,12 @@ void ScheduleDAG::EmitSchedule() {
// If this is the first basic block in the function, and if it has live ins // If this is the first basic block in the function, and if it has live ins
// that need to be copied into vregs, emit the copies into the top of the // that need to be copied into vregs, emit the copies into the top of the
// block before emitting the code for the block. // block before emitting the code for the block.
MachineFunction &MF = DAG.getMachineFunction(); if (&MF->front() == BB) {
if (&MF.front() == BB) {
for (MachineRegisterInfo::livein_iterator LI = RegInfo.livein_begin(), for (MachineRegisterInfo::livein_iterator LI = RegInfo.livein_begin(),
E = RegInfo.livein_end(); LI != E; ++LI) E = RegInfo.livein_end(); LI != E; ++LI)
if (LI->second) { if (LI->second) {
const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second); const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second);
TII->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second, TII->copyRegToReg(*MF->begin(), MF->begin()->end(), LI->second,
LI->first, RC, RC); LI->first, RC, RC);
} }
} }