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Teach legalize to deal with targets that don't support some SEXTLOAD/ZEXTLOADs 

llvm-svn: 21212
This commit is contained in:
Chris Lattner 2005-04-10 22:54:25 +00:00
parent 672fe7267b
commit a3b7ef05f4
1 changed files with 38 additions and 13 deletions
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51
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -442,22 +442,47 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
case ISD::EXTLOAD:
case ISD::SEXTLOAD:
case ISD::ZEXTLOAD:
case ISD::ZEXTLOAD: {
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
if (Tmp1 != Node->getOperand(0) ||
Tmp2 != Node->getOperand(1))
Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2,
cast<MVTSDNode>(Node)->getExtraValueType());
else
Result = SDOperand(Node, 0);
// Since loads produce two values, make sure to remember that we legalized
// both of them.
AddLegalizedOperand(SDOperand(Node, 0), Result);
AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
MVT::ValueType SrcVT = cast<MVTSDNode>(Node)->getExtraValueType();
switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
case TargetLowering::Promote:
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal:
if (Tmp1 != Node->getOperand(0) ||
Tmp2 != Node->getOperand(1))
Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0),
Tmp1, Tmp2, SrcVT);
else
Result = SDOperand(Node, 0);
// Since loads produce two values, make sure to remember that we legalized
// both of them.
AddLegalizedOperand(SDOperand(Node, 0), Result);
AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
break;
case TargetLowering::Expand:
assert(Node->getOpcode() != ISD::EXTLOAD &&
"EXTLOAD should always be supported!");
// Turn the unsupported load into an EXTLOAD followed by an explicit
// zero/sign extend inreg.
Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0),
Tmp1, Tmp2, SrcVT);
unsigned ExtOp = Node->getOpcode() == ISD::SEXTLOAD ?
ISD::SIGN_EXTEND_INREG : ISD::ZERO_EXTEND_INREG;
SDOperand ValRes = DAG.getNode(ExtOp, Result.getValueType(),
Result, SrcVT);
AddLegalizedOperand(SDOperand(Node, 0), ValRes);
AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
if (Op.ResNo)
return Result.getValue(1);
return ValRes;
}
assert(0 && "Unreachable");
}
case ISD::EXTRACT_ELEMENT:
// Get both the low and high parts.
ExpandOp(Node->getOperand(0), Tmp1, Tmp2);