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Change RET node to include signness information of the return values. i.e. 

RET chain, value1, sign1, value2, sign2, ...

llvm-svn: 28510
This commit is contained in:
Evan Cheng 2006-05-26 23:10:12 +00:00
parent a2e9953c54
commit a3add0fea8
6 changed files with 13 additions and 13 deletions
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4
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -62,8 +62,8 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
abort();
case 1:
return SDOperand(); // ret void is legal
case 2:
Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(1), SDOperand());
case 3:
Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(2), SDOperand());
break;
}

2
llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -231,7 +231,7 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
Select(Chain, N->getOperand(0)); // Token chain.
SDOperand InFlag(0,0);
if (N->getNumOperands() == 2) {
if (N->getNumOperands() == 3) {
SDOperand Val;
Select(Val, N->getOperand(1));
if (N->getOperand(1).getValueType() == MVT::i64) {

2
llvm/lib/Target/IA64/IA64ISelLowering.cpp
View File

@ -562,7 +562,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS,
AR_PFSVal);
return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal);
case 2: {
case 3: {
// Copy the result into the output register & restore ar.pfs
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg = MVT::isInteger(ArgVT) ? IA64::r8 : IA64::F8;

6
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1160,7 +1160,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
abort();
case 1:
return SDOperand(); // ret void is legal
case 2: {
case 3: {
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg;
if (MVT::isVector(ArgVT))
@ -1180,8 +1180,8 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
DAG.getMachineFunction().addLiveOut(ArgReg);
break;
}
case 3:
Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2),
case 5:
Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3),
SDOperand());
Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
// If we haven't noted the R3+R4 are live out, do so now.

6
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -857,7 +857,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
abort();
case 1:
return SDOperand(); // ret void is legal
case 2: {
case 3: {
unsigned ArgReg;
switch(Op.getOperand(1).getValueType()) {
default: assert(0 && "Unknown type to return!");
@ -869,8 +869,8 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
SDOperand());
break;
}
case 3:
Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(2),
case 5:
Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3),
SDOperand());
Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
break;

6
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -3326,7 +3326,7 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
case 1: // ret void.
return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
case 2: {
case 3: {
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
if (MVT::isVector(ArgVT)) {
@ -3394,13 +3394,13 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
}
break;
}
case 3:
case 5:
if (DAG.getMachineFunction().liveout_empty()) {
DAG.getMachineFunction().addLiveOut(X86::EAX);
DAG.getMachineFunction().addLiveOut(X86::EDX);
}
Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(2),
Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(3),
SDOperand());
Copy = DAG.getCopyToReg(Copy, X86::EAX,Op.getOperand(1),Copy.getValue(1));
break;