Add implementation for EmulateInstructionARM::EmulateB() and fixed two typos in g_thumb_opcodes
as pointed out By Caroline. Refactored a little bit by adding two new helper methods to the EmulateInstructionARM class: o BranchWritePC() o BXWritePC() llvm-svn: 125059
This commit is contained in:
Johnny Chen
parent
55fc1d0b3e
commit
a3990398a3
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@ -779,24 +779,24 @@ EmulateInstructionARM::EmulateBLXImmediate (ARMEncoding encoding)
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uint32_t I2 = !(J2 ^ S);
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uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10H << 12) + (imm10L << 2);
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imm32 = llvm::SignExtend32<25>(imm25);
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target = (pc & 0xfffffffc) + 4 + imm32;
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context.arg1 = eModeARM; // target instruction set
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context.arg2 = 4 + imm32; // signed offset
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target = ((pc + 4) & 0xfffffffc) + imm32;
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context.arg1 = 4 + imm32; // signed offset
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context.arg2 = eModeARM; // target instruction set
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break;
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}
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case eEncodingA2:
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lr = pc + 4; // return address
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imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 | Bits32(opcode, 24, 24) << 1);
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target = pc + 8 + imm32;
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context.arg1 = eModeThumb; // target instruction set
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context.arg2 = 8 + imm32; // signed offset
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context.arg1 = 8 + imm32; // signed offset
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context.arg2 = eModeThumb; // target instruction set
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break;
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default:
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return false;
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}
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if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
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return false;
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if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target))
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if (!BranchWritePC(context, target))
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return false;
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}
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return true;
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@ -858,19 +858,11 @@ EmulateInstructionARM::EmulateBLXRm (ARMEncoding encoding)
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default:
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return false;
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}
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bool toThumb;
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if (BitIsSet(target, 0))
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toThumb = true;
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else if (BitIsClear(target, 1))
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toThumb = false;
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else
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return false; // address<1:0> == ‘10’ => UNPREDICTABLE
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context.arg0 = eRegisterKindDWARF;
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context.arg1 = dwarf_r0 + Rm;
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context.arg2 = toThumb ? eModeThumb : eModeARM;
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if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
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return false;
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if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target))
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if (!BXWritePC(context, target))
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return false;
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}
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return true;
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@ -1394,7 +1386,72 @@ EmulateInstructionARM::EmulateB (ARMEncoding encoding)
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if (!success)
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return false;
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return false;
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if (ConditionPassed())
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{
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EmulateInstruction::Context context = { EmulateInstruction::eContextRelativeBranchImmediate, 0, 0, 0};
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const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
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addr_t target; // target address
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if (!success)
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return false;
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int32_t imm32; // PC-relative offset
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switch (encoding) {
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case eEncodingT1:
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// The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
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imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1);
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target = pc + 4 + imm32;
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context.arg1 = 4 + imm32; // signed offset
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context.arg2 = eModeThumb; // target instruction set
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break;
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case eEncodingT2:
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imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0));
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target = pc + 4 + imm32;
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context.arg1 = 4 + imm32; // signed offset
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context.arg2 = eModeThumb; // target instruction set
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break;
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case eEncodingT3:
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// The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
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{
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uint32_t S = Bits32(opcode, 26, 26);
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uint32_t imm6 = Bits32(opcode, 21, 16);
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uint32_t J1 = Bits32(opcode, 13, 13);
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uint32_t J2 = Bits32(opcode, 11, 11);
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uint32_t imm11 = Bits32(opcode, 10, 0);
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uint32_t imm21 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) + (imm11 << 1);
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imm32 = llvm::SignExtend32<21>(imm21);
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target = pc + 4 + imm32;
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context.arg1 = eModeThumb; // target instruction set
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context.arg2 = 4 + imm32; // signed offset
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break;
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}
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case eEncodingT4:
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{
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uint32_t S = Bits32(opcode, 26, 26);
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uint32_t imm10 = Bits32(opcode, 25, 16);
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uint32_t J1 = Bits32(opcode, 13, 13);
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uint32_t J2 = Bits32(opcode, 11, 11);
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uint32_t imm11 = Bits32(opcode, 10, 0);
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uint32_t I1 = !(J1 ^ S);
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uint32_t I2 = !(J2 ^ S);
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uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) + (imm11 << 1);
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imm32 = llvm::SignExtend32<25>(imm25);
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target = pc + 4 + imm32;
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context.arg1 = eModeThumb; // target instruction set
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context.arg2 = 4 + imm32; // signed offset
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break;
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}
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case eEncodingA1:
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imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
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target = pc + 8 + imm32;
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context.arg1 = eModeARM; // target instruction set
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context.arg2 = 8 + imm32; // signed offset
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break;
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default:
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return false;
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}
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if (!BranchWritePC(context, target))
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return false;
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}
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return true;
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}
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EmulateInstructionARM::ARMOpcode*
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@ -1530,8 +1587,8 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode)
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// To resolve ambiguity, "b<c> #imm8" should come after "svc #imm8".
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{ 0xfffff000, 0x0000d000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateB, "b<c> #imm8 (outside IT)"},
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{ 0xffff8000, 0x0000e000, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateB, "b #imm11 (outside or last in IT)"},
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{ 0xf800d000, 0x00008000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateB, "b<c>.w #imm8 (outside IT)"},
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{ 0xf800d000, 0x00009000, ARMV6T2_ABOVE, eEncodingT4, eSize32, &EmulateInstructionARM::EmulateB, "b.w #imm8 (outside or last in IT)"}
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{ 0xf800d000, 0xf0008000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateB, "b<c>.w #imm8 (outside IT)"},
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{ 0xf800d000, 0xf0009000, ARMV6T2_ABOVE, eEncodingT4, eSize32, &EmulateInstructionARM::EmulateB, "b.w #imm8 (outside or last in IT)"}
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};
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@ -1628,40 +1685,6 @@ EmulateInstructionARM::ReadInstruction ()
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return success;
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}
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uint32_t
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EmulateInstructionARM::CurrentCond ()
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{
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switch (m_inst_mode)
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{
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default:
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case eModeInvalid:
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break;
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case eModeARM:
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return UnsignedBits(m_inst.opcode.inst32, 31, 28);
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case eModeThumb:
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// For T1 and T3 encodings of the Branch instruction, it returns the 4-bit
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// 'cond' field of the encoding.
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if (m_inst.opcode_type == eOpcode16 &&
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Bits32(m_inst.opcode.inst16, 15, 12) == 0x0d &&
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Bits32(m_inst.opcode.inst16, 11, 7) != 0x0f)
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{
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return Bits32(m_inst.opcode.inst16, 11, 7);
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}
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else if (m_inst.opcode_type == eOpcode32 &&
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Bits32(m_inst.opcode.inst32, 31, 27) == 0x1e &&
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Bits32(m_inst.opcode.inst32, 15, 14) == 0x02 &&
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Bits32(m_inst.opcode.inst32, 12, 12) == 0x00 &&
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Bits32(m_inst.opcode.inst32, 25, 22) <= 0x0d)
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{
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return Bits32(m_inst.opcode.inst32, 25, 22);
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}
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return m_it_session.GetCond();
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}
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return UINT32_MAX; // Return invalid value
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}
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bool
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EmulateInstructionARM::ConditionPassed ()
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{
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@ -1705,6 +1728,88 @@ EmulateInstructionARM::ConditionPassed ()
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return result;
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}
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uint32_t
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EmulateInstructionARM::CurrentCond ()
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{
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switch (m_inst_mode)
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{
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default:
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case eModeInvalid:
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break;
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case eModeARM:
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return UnsignedBits(m_inst.opcode.inst32, 31, 28);
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case eModeThumb:
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// For T1 and T3 encodings of the Branch instruction, it returns the 4-bit
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// 'cond' field of the encoding.
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if (m_inst.opcode_type == eOpcode16 &&
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Bits32(m_inst.opcode.inst16, 15, 12) == 0x0d &&
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Bits32(m_inst.opcode.inst16, 11, 7) != 0x0f)
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{
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return Bits32(m_inst.opcode.inst16, 11, 7);
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}
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else if (m_inst.opcode_type == eOpcode32 &&
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Bits32(m_inst.opcode.inst32, 31, 27) == 0x1e &&
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Bits32(m_inst.opcode.inst32, 15, 14) == 0x02 &&
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Bits32(m_inst.opcode.inst32, 12, 12) == 0x00 &&
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Bits32(m_inst.opcode.inst32, 25, 22) <= 0x0d)
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{
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return Bits32(m_inst.opcode.inst32, 25, 22);
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}
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return m_it_session.GetCond();
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}
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return UINT32_MAX; // Return invalid value
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}
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// API client must pass in a context whose arg2 field contains the target instruction set.
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bool
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EmulateInstructionARM::BranchWritePC (const Context &context, uint32_t addr)
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{
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addr_t target;
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// Chech the target instruction set.
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switch (context.arg2)
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{
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default:
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assert(0 && "BranchWritePC expects context.arg1 with either eModeARM or eModeThumb");
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return false;
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case eModeARM:
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target = addr & 0xfffffffc;
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break;
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case eModeThumb:
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target = addr & 0xfffffffe;
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break;
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}
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if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target))
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return false;
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return false;
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}
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// As a side effect, BXWritePC sets context.arg2 to eModeARM or eModeThumb by inspecting addr.
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bool
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EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr)
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{
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addr_t target;
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if (BitIsSet(addr, 0))
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{
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target = addr & 0xfffffffe;
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context.arg2 = eModeThumb;
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}
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else if (BitIsClear(addr, 1))
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{
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target = addr & 0xfffffffc;
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context.arg2 = eModeARM;
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}
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else
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return false; // address<1:0> == '10' => UNPREDICTABLE
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if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target))
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return false;
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return false;
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}
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bool
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EmulateInstructionARM::EvaluateInstruction ()
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@ -145,6 +145,12 @@ public:
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uint32_t
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CurrentCond ();
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bool
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BranchWritePC(const Context &context, uint32_t addr);
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bool
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BXWritePC(Context &context, uint32_t addr);
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protected:
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// Typedef for the callback function used during the emulation.
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