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Rename some subtarget features. A CPU now can *have* 64-bit instructions, 

can in 32-bit mode we can choose to optionally *use* 64-bit registers.

llvm-svn: 28824
This commit is contained in:
Chris Lattner 2006-06-16 17:34:12 +00:00
parent 29052c849f
commit a35f306740
4 changed files with 12 additions and 12 deletions
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6
llvm/lib/Target/PowerPC/PPC.td
View File

@ -19,10 +19,10 @@ include "../Target.td"
// PowerPC Subtarget features.
//
def Feature64Bit : SubtargetFeature<"64bit","Is64Bit", "true",
def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
"Enable 64-bit instructions">;
def Feature64BitRegs : SubtargetFeature<"64bitregs","Has64BitRegs", "true",
"Enable 64-bit registers [beta]">;
def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
"Enable 64-bit registers usage for ppc32 [beta]">;
def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
"Enable Altivec instructions">;
def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true",

6
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -146,7 +146,7 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
// We want to custom lower some of our intrinsics.
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
// They also have instructions for converting between i64 and fp.
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
@ -163,7 +163,7 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
}
if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
// 64 bit PowerPC implementations can support i64 types directly
addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
// BUILD_PAIR can't be handled natively, and should be expanded to shl/or
@ -2227,7 +2227,7 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
switch (N->getOpcode()) {
default: break;
case ISD::SINT_TO_FP:
if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
// Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
// We allow the src/dst to be either f32/f64, but the intermediate

4
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
View File

@ -73,8 +73,8 @@ PPCSubtarget::PPCSubtarget(const Module &M, const std::string &FS, bool is64Bit)
: StackAlignment(16)
, InstrItins()
, IsGigaProcessor(false)
, Is64Bit(false)
, Has64BitRegs(false)
, Has64BitSupport(false)
, Use64BitRegs(false)
, HasAltivec(false)
, HasFSQRT(false)
, HasSTFIWX(false)

8
llvm/lib/Target/PowerPC/PPCSubtarget.h
View File

@ -33,8 +33,8 @@ protected:
/// Used by the ISel to turn in optimizations for POWER4-derived architectures
bool IsGigaProcessor;
bool Is64Bit;
bool Has64BitRegs;
bool Has64BitSupport;
bool Use64BitRegs;
bool HasAltivec;
bool HasFSQRT;
bool HasSTFIWX;
@ -66,12 +66,12 @@ public:
bool hasFSQRT() const { return HasFSQRT; }
bool hasSTFIWX() const { return HasSTFIWX; }
bool has64BitRegs() const { return Has64BitRegs; }
bool use64BitRegs() const { return Use64BitRegs; }
bool hasAltivec() const { return HasAltivec; }
bool isAIX() const { return IsAIX; }
bool isDarwin() const { return IsDarwin; }
bool is64Bit() const { return Is64Bit; }
bool has64BitSupport() const { return Has64BitSupport; }
bool isGigaProcessor() const { return IsGigaProcessor; }
};
} // End llvm namespace