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[Mips] Fix for BBIT octeon instruction 

This patch enables control flow optimization for
variations of BBIT instruction. In this case
optimization removes unnecessary branch after
BBIT instruction.

Differential Revision: https://reviews.llvm.org/D35359

llvm-svn: 309679
This commit is contained in:
Strahinja Petrovic 2017-08-01 13:42:45 +00:00
parent fa76b49cef
commit a2b4748bdc
2 changed files with 28 additions and 13 deletions
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8
llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
View File

@ -451,6 +451,10 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
case Mips::BGEZC64: return Mips::BLTZC64;
case Mips::BLTZC64: return Mips::BGEZC64;
case Mips::BLEZC64: return Mips::BGTZC64;
case Mips::BBIT0: return Mips::BBIT1;
case Mips::BBIT1: return Mips::BBIT0;
case Mips::BBIT032: return Mips::BBIT132;
case Mips::BBIT132: return Mips::BBIT032;
}
}
@ -541,7 +545,9 @@ unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
Opc == Mips::BGEC64 || Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 ||
Opc == Mips::BLTUC64 || Opc == Mips::BGTZC64 ||
Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 ||
Opc == Mips::BLEZC64 || Opc == Mips::BC) ? Opc : 0;
Opc == Mips::BLEZC64 || Opc == Mips::BC || Opc == Mips::BBIT0 ||
Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
Opc == Mips::BBIT132) ? Opc : 0;
}
void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,

33
llvm/test/CodeGen/Mips/octeon.ll
View File

@ -1,5 +1,6 @@
; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON
; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64
; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon -relocation-model=pic | FileCheck %s -check-prefixes=ALL,OCTEON-PIC
define i64 @addi64(i64 %a, i64 %b) nounwind {
entry:
@ -88,10 +89,12 @@ entry:
ret i64 %res2
}
define i64 @bbit0(i64 %a) nounwind {
define i64 @bbit1(i64 %a) nounwind {
entry:
; ALL-LABEL: bbit0:
; OCTEON: bbit0 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; ALL-LABEL: bbit1:
; OCTEON: bbit1 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; OCTEON-PIC-NOT: b {{[[:space:]].*}}
; OCTEON-NOT: j {{[[:space:]].*}}
; MIPS64: andi $[[T0:[0-9]+]], $4, 8
; MIPS64: bnez $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]]
%bit = and i64 %a, 8
@ -104,10 +107,12 @@ endif:
ret i64 12
}
define i64 @bbit032(i64 %a) nounwind {
define i64 @bbit132(i64 %a) nounwind {
entry:
; ALL-LABEL: bbit032:
; OCTEON: bbit032 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; ALL-LABEL: bbit132:
; OCTEON: bbit132 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; OCTEON-PIC-NOT: b {{[[:space:]].*}}
; OCTEON-NOT: j {{[[:space:]].*}}
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]
@ -122,10 +127,12 @@ endif:
ret i64 12
}
define i64 @bbit1(i64 %a) nounwind {
define i64 @bbit0(i64 %a) nounwind {
entry:
; ALL-LABEL: bbit1:
; OCTEON: bbit1 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; ALL-LABEL: bbit0:
; OCTEON: bbit0 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; OCTEON-PIC-NOT: b {{[[:space:]].*}}
; OCTEON-NOT: j {{[[:space:]].*}}
; MIPS64: andi $[[T0:[0-9]+]], $4, 8
; MIPS64: beqz $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]]
%bit = and i64 %a, 8
@ -138,10 +145,12 @@ endif:
ret i64 12
}
define i64 @bbit132(i64 %a) nounwind {
define i64 @bbit032(i64 %a) nounwind {
entry:
; ALL-LABEL: bbit132:
; OCTEON: bbit132 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; ALL-LABEL: bbit032:
; OCTEON: bbit032 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; OCTEON-PIC-NOT: b {{[[:space:]].*}}
; OCTEON-NOT: j {{[[:space:]].*}}
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]