diff --git a/llvm/test/CodeGen/X86/adde-carry.ll b/llvm/test/CodeGen/X86/adde-carry.ll index e86adf4b1784..4d6ad82a2631 100644 --- a/llvm/test/CodeGen/X86/adde-carry.ll +++ b/llvm/test/CodeGen/X86/adde-carry.ll @@ -1,6 +1,14 @@ -; RUN: llc -march=x86-64 < %s | FileCheck %s -check-prefix=CHECK-64 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s define void @a(i64* nocapture %s, i64* nocapture %t, i64 %a, i64 %b, i64 %c) nounwind { +; CHECK-LABEL: a: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addq %rcx, %rdx +; CHECK-NEXT: adcq $0, %r8 +; CHECK-NEXT: movq %r8, (%rdi) +; CHECK-NEXT: movq %rdx, (%rsi) +; CHECK-NEXT: retq entry: %0 = zext i64 %a to i128 %1 = zext i64 %b to i128 @@ -14,7 +22,28 @@ entry: %8 = trunc i128 %2 to i64 store i64 %8, i64* %t, align 8 ret void - -; CHECK-64: addq -; CHECK-64: adcq $0 +} + +define i64 @pr31719(i64 %.elt, i64 %.elt24, i64 %t1) { +; CHECK-LABEL: pr31719: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addq %rdx, %rdi +; CHECK-NEXT: sbbq %rax, %rax +; CHECK-NEXT: andl $1, %eax +; CHECK-NEXT: addq %rsi, %rax +; CHECK-NEXT: sbbq %rax, %rax +; CHECK-NEXT: andl $1, %eax +; CHECK-NEXT: retq +entry: + %t2 = zext i64 %t1 to i128 + %t3 = zext i64 %.elt to i128 + %t4 = add nuw nsw i128 %t2, %t3 + %t5 = lshr i128 %t4, 64 + %t6 = zext i64 %.elt24 to i128 + %t7 = add nuw nsw i128 0, %t6 + %t8 = add nuw nsw i128 %t7, %t5 + %t9 = lshr i128 %t8, 64 + %t10 = add nuw nsw i128 0, %t9 + %t11 = trunc i128 %t10 to i64 + ret i64 %t11 }