Fix a regression from r147481.
Original commit message from r147481: DAGCombine for transforming 128->256 casts into a vmovaps, rather then a vxorps + vinsertf128 pair if the original vector came from a load. Fix: Unaligned loads need to generate a vmovups. rdar://10974078 llvm-svn: 152366
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@ -218,6 +218,11 @@ def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return cast<LoadSDNode>(N)->getAlignment() >= 16;
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return cast<LoadSDNode>(N)->getAlignment() >= 16;
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}]>;
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}]>;
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// Like 'X86vzload', but always requires 128-bit vector alignment.
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def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
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return cast<MemSDNode>(N)->getAlignment() >= 16;
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}]>;
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// Like 'load', but always requires 256-bit vector alignment.
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// Like 'load', but always requires 256-bit vector alignment.
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def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return cast<LoadSDNode>(N)->getAlignment() >= 32;
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return cast<LoadSDNode>(N)->getAlignment() >= 32;
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@ -4820,8 +4820,10 @@ let Predicates = [HasSSE2], AddedComplexity = 20 in {
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}
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}
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let Predicates = [HasAVX] in {
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let Predicates = [HasAVX] in {
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def : Pat<(v4i64 (X86vzload addr:$src)),
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def : Pat<(v4i64 (alignedX86vzload addr:$src)),
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(SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
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(SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
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def : Pat<(v4i64 (X86vzload addr:$src)),
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(SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
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}
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}
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//===---------------------------------------------------------------------===//
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//===---------------------------------------------------------------------===//
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@ -135,3 +135,15 @@ define <4 x i32> @test15(<2 x i32>%x) nounwind readnone {
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ret <4 x i32>%x1
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ret <4 x i32>%x1
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}
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}
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; rdar://10974078
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define <8 x float> @test16(float* nocapture %f) nounwind uwtable readonly ssp {
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entry:
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%0 = bitcast float* %f to <4 x float>*
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%1 = load <4 x float>* %0, align 8
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; CHECK: test16
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; CHECK: vmovups
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; CHECK-NOT: vxorps
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; CHECK-NOT: vinsertf128
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%shuffle.i = shufflevector <4 x float> %1, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
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ret <8 x float> %shuffle.i
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}
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